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mc9s12h256 device user guide ?v01.20 1 mc9s12h256 device user guide v01.20 covers also MC9S12H128 original release date: 29 sep 2000 revised: 28 jul 2008 freescale semiconductor inc.
freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design. freescale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a situation where personal injury or death may occur. should buyer purchase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part. document number 9s12h256bdgv1/d 2 revision history version number revision date effective date author description of changes v01.00 07 mar 2001 03 apr 2001 initial version. v01.01 10 mai 2001 10 may 2001 - minor formal corrections - changed atd coupling ratio to10 -2 - changed v dd5 to 4.5v v01.02 14 may 2001 14 may 2001 - removed 112-pin package references - changed atd electrical characteristics separate coupling ratio for positive and negative bulk current injection v01.03 30 may 2001 30 may 2001 - reinserted 112-pin package information. v01.04 11 jun 2001 11 jun 2001 - removed srsv2 comment from preface - corrected reset pin to active low in table 2-1 v01.05 18 jun 2001 18 jun 2001 - adapted style and wording to 9dp256 device user guide - minor format and wording improvements - added sram data retention disclaimer v01.06 28 jun 2001 28 jun 2001 - changed oscillator characteristics t cqout max 2.5s and replaced clock monitor time-out by clock monitor failure assert frequency - changed self clock mode frequency min 1mhz and max 5.5mhz - changed i ddps (rti and cop disabled) to 400 a - corrected typo in figure 2-1 pin 76: pk3 -> pk2 v01.07 12 jul 2001 12 jul 2001 - added t extr and t extf to oscillator characteristics - added typ value for t uposc - corrected t extl and t exth values - updated thermal resistances as per thermal simulation report, july 10, 2001 v01.08 16 jul 2001 16 jul 2001 - updated eeprom size - added dc cutoff capacitor into layout proposals v01.09 03 aug 2001 03 aug 2001 - minor updates v01.10 29 aug 2001 29 aug 2001 - updated electrical spec
mc9s12h256 device user guide ?v01.20 3 v01.11 11 oct 2001 11 oct 2001 - replaced references w.r.t. new family name hcs12. - corrected xclks reference in crg electrical spec. v01.12 07 nov 2001 07 nov 2001 - added ?owered by?column in pin list table v01.13 08 mar 2002 08 mar 2002 - new document numbering - removed document order number except from cover sheet - updated min vdd, vddpll - updated currents on v oh ,v ol for standard pins - updated c in , i dds , i ref , c ins , t extl , t exth - included missing lcd electrical spec - updated nvm spec v01.14 16 dec 2002 16 dec 2002 - updated input leakage - updated slew rate spec on pu,pv, pw - updated supply currents - included 1k78x - added detailed register map v01.15 31 mar 2003 31 mar 2003 - added k 1 max value - added chragepump current min/max values v01.16 05 nov 2003 05 nov 2003 - corrected pinout problem in lqfp112 layout proposal v01.17 04 aug 2004 04 aug 2004 - added MC9S12H128 v01.18 13 aug 2004 13 aug 2004 - added internal pull resistor columns to signal properties table v01.19 05 nov 2004 05 nov 2004 - changed spi0 to spi, atd0 to atd v01.20 28 jul 2008 28 jul 2008 - changed pu,pv,pw rise/fall times in epp package at cold. version number revision date effective date author description of changes
mc9s12h256 device user guide ?v01.20 4
mc9s12h256 device user guide ?v01.20 5 section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.1 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.2 signal properties summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.1 extal, xtal ?oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.2 reset ?external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.3 test ?test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.4 xfc ?pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.5 bkgd / taghi / modc ?background debug, tag high, and mode pin. . . . . . . . . . . . . 60 2.3.6 pad[15:8] / an[15:8] ?port ad input pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.7 pad[7:0] / an[7:0] ?port ad input pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.8 pa[7:0] / fp[15:8] / addr[15:8] / data[15:8] ?port a i/o pins . . . . . . . . . . . . . . . . . . 60 2.3.9 pb[7:0] / fp[7:0] / addr[7:0] / data[7:0] ?port b i/o pins . . . . . . . . . . . . . . . . . . . . . . 61 2.3.10 pe7 / fp22 / xclks / noacc ?port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.11 pe6 / modb / ipipe1 ?port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.12 pe5 / moda / ipipe0 ?port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.13 pe4 / eclk ?port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.14 pe3 / fp21 / lstrb / taglo ?port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.15 pe2 / fp20 / r/w ?port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 2.3.16 pe1 / irq ?port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.17 pe0 / xirq ?port e input pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.18 ph[7:0] / kwh[7:0] ?port h i/o pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.19 pj[3:0] / kwj[3:0] ?port j i/o pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.20 pk7 / fp23 / ecs / romone ?port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.21 pk[3:0] / bp[3:0] / xaddr[17:14] ?port k i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.22 pl[7:4] / fp[31:28] ?port l i/o pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.23 pl[3:0] / fp[19:16] ?port l i/o pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
mc9s12h256 device user guide ?v01.20 6 2.3.24 pm5 / txcan1 ?port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.25 pm4 / rxcan1 ?port m i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.26 pm3 / txcan0 ?port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.27 pm2 / rxcan0 ?port m i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.28 pm1 / scl ?port m i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.3.29 pm0 / sda ?port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.3.30 pp[5:2] / pwm[5:2] ?port p i/o pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.31 pp[1:0] / pwm[1:0] ?port p i/o pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.32 ps7 / ss ?port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.33 ps6 / sck ?port s i/o pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.34 ps5 / mosi ?port s i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.35 ps4 / miso ?port s i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.36 ps3 / txd1 ?port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.37 ps2 / rxd1 ?port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.38 ps1 / txd0 ?port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.3.39 ps0 / rxd0 ?port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.3.40 pt[7:4] / ioc[7:4] ?port t i/o pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.41 pt[3:0] / ioc[3:0] / fp[27:24] ?port t i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.42 pu[7:4] / m1c1p, m1c1m, m1c0p, m1c0m ?port u i/o pins [7:4] . . . . . . . . . . . . . . . . 65 2.3.43 pu[3:0] / m0c1p, m0c1m, m0c0p, m0c0m ?port u i/o pins [3:0] . . . . . . . . . . . . . . . . 65 2.3.44 pv[7:4] / m3c1p, m3c1m, m3c0p, m3c0m ?port v i/o pins [7:4] . . . . . . . . . . . . . . . . 65 2.3.45 pv[3:0] / m2c1p, m2c1m, m2c0p, m2c0m ?port v i/o pins [3:0] . . . . . . . . . . . . . . . . 66 2.3.46 pw[7:4] / m5c1p, m5c1m, m5c0p, m5c0m ?port w i/o pins [7:4] . . . . . . . . . . . . . . . 66 2.3.47 pw[3:0] / m4c1p, m4c1m, m4c0p, m4c0m ?port w i/o pins [3:0] . . . . . . . . . . . . . . . 66 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.1 vddr ?external power pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.2 vddx1, vddx2, vssx1, vssx2 ?external power and ground pins . . . . . . . . . . . . . . . 66 2.4.3 vdd1, vss1, vss2 ?core power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.4 vdda, vssa ?power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.5 vddm1, vddm2, vddm3 ?power supply pins for motor 0 to 5 . . . . . . . . . . . . . . . . . . 67 2.4.6 vssm1, vssm2, vssm3 ?ground pins for motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.7 vlcd ?power supply reference pin for lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.8 vrh, vrl ?atd reference voltage input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.9 vddpll, vsspll ?power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 3 system clock description
mc9s12h256 device user guide ?v01.20 7 3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.1 normal operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.2 special operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2.3 test operating mode (freescale use only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 section 6 hcs12 core block description section 7 clock and reset generator (crg) block description 7.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.1.1 xclks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 8 timer (tim) block description section 9 analog to digital converter (atd) block description section 10 inter-ic bus (iic) block description section 11 serial communications interface (sci) block description section 12 serial peripheral interface (spi) block description
mc9s12h256 device user guide ?v01.20 8 section 13 pulse width modulator (pwm) block description section 14 flash eeprom 256k block description section 15 eeprom 4k block description section 16 ram block description section 17 liquid crystal display driver (lcd) block description section 18 mscan block description section 19 pwm motor control (mc) block description section 20 port integration module (pim) block description section 21 voltage regulator (vreg) block description 21.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.1.1 vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21.2 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.1.3 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.2.1 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
mc9s12h256 device user guide ?v01.20 9 a.2.3 atd accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 a.3 nvm, flash and eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 a.3.1 nvm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 a.3.2 nvm reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 a.4 reset, oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.4.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.4.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 a.4.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 a.5 mscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 a.6 spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 a.6.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 a.6.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 a.7 lcd_32f4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 a.8 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 a.8.1 general muxed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 appendix b package information b.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 b.2 112-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 b.3 144-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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mc9s12h256 device user guide ?v01.20 11 figure 1-1 mc9s12h256 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 1-2 MC9S12H128 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 1-3 mc9s12h256 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 1-4 MC9S12H128 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 2-1 pin assignments in 112-pin lqfp for mc9s12h256 and MC9S12H128 . . . . . . . . . . 56 figure 2-2 pin assignments in 144-pin lqfp for mc9s12h256 . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 3-1 clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21-1 lqfp112 recommended pcb layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 21-2 lqfp144 recommended pcb layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure a-1 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure a-2 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure a-3 jitter definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure a-4 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure a-5 spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure a-6 spi master timing (cpha =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure a-7 spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure a-8 spi slave timing (cpha =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure a-9 general external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure b-1 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . 126 figure b-2 144-pin lqfp mechanical dimensions (case no. 918-03) . . . . . . . . . . . . . . . . . . . . . 127
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mc9s12h256 device user guide ?v01.20 13 table 0-1 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 1-1 device memory map mc9s12h256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 1-2 device memory map MC9S12H128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 1-3 detailed mscan foreground receive and transmit buffer layout. . . . . . . . . . . . . . . . . 44 table 1-4 detailed mscan foreground receive and transmit buffer layout. . . . . . . . . . . . . . . . . 46 table 1-5 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 1-6 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 5-1 reset and interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 21-1 recommended components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table a-2 esd and latch-up test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table a-7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table a-8 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table a-9 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table a-10 atd conversion performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 table a-11 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table a-12 nvm reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table a-13 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table a-14 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table a-15 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table a-16 mscan wake-up pulse characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table a-17 spi master mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table a-18 spi slave mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 lcd_32f4b driver electrical characteristics 119 table a-20 expanded bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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mc9s12h256 device user guide ?v01.20 15 preface the device user guide provides information about the mc9s12h256 and MC9S12H128 device made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes the hcs12 core user guide and all the individual block user guides of the implemented modules. in an effort to reduce redundancy all module specific information is located only in the respective block user guide. if applicable, special implementation details of the module are given in the block description sections of this document. see table 0-1 for names and versions of the referenced documents throughout the device user guide. table 0-1 document references user guide version document order number hcs12 v1.5 core user guide 1.2 hcs12coreug crg block user guide v02 s12crgv2/d tim_16b8c block user guide v01 s12tim16b8cv1/d atd_10b16c block user guide v02 s12atd10b16cv2/d iic block user guide v02 s12iicv2/d sci block user guide v02 s12sciv2/d spi block user guide v02 s12spiv2/d pwm_8b6c block user guide v01 s12pwm8b6cv1/d fts256k block user guide v02 s12fts256kv2/d eets4k block user guide v02 s12eets4kv2/d lcd_32f4b block user guide v01 s12lcd32f4bv1/d mscan block user guide v02 s12mscanv2/d mc_10b12c block user guide v02 s12mc10b12cv2/d pim_9h256 block user guide v01 s12pimh256v1/d vreg block user guide v01 s12vregv1/d
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mc9s12h256 device user guide ?v01.20 17 section 1 introduction 1.1 overview the mc9s12h256 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (hcs12 cpu), 256k bytes of flash eeprom, 12k bytes of ram, 4k bytes of eeprom, two asynchronous serial communications interfaces (sci), a serial peripheral interface (spi), an iic-bus interface (iic), an 8-channel 16-bit timer (tim), a 16-channel, 10-bit analog-to-digital converter (atd), a six-channel pulse width modulator (pwm), and two can 2.0 a, b software compatible modules (mscan). the MC9S12H128 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (hcs12 cpu), 128k bytes of flash eeprom, 6k bytes of ram, 2k bytes of eeprom, one asynchronous serial communications interface (sci), a serial peripheral interface (spi), an iic-bus interface (iic), an 8-channel 16-bit timer (tim), a 8-channel, 10-bit analog-to-digital converter (atd), a two-channel pulse width modulator (pwm), and two can 2.0 a, b software compatible modules (mscan). in addition, it features a 32x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (mc) consisting of 24 high current outputs suited to drive up to 6 stepper motors. system resource mapping, clock generation, interrupt control, and bus interfacing are managed by the hcs12 core. the mc9s12h256 has full 16-bit data paths throughout. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, 12 general purpose i/o pins are available with interrupt and wake-up capability from stop or wait mode. 1.2 features hcs12 core 16-bit hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmer? model identical to m68hc11 iii. 20-bit alu iv. instruction queue v. enhanced indexed addressing mebi (multiplexed external bus interface) mmc (module mapping control) int (interrupt control) bkp (breakpoints)
mc9s12h256 device user guide ?v01.20 18 bdm (background debug mode) crg (low current oscillator, pll, reset, clocks, cop watchdog, real time interrupt, clock monitor) 8-bit and 4-bit ports with interrupt functionality digital filtering programmable rising or falling edge trigger memory 128k, 256k flash eeprom 2k, 4k byte eeprom 6k, 12k byte ram analog-to-digital converter 8, 16 channels, 10-bit resolution external conversion trigger capability two 1m bit per second, can 2.0 a, b software compatible modules five receive and three transmit buffers flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit four separate interrupt channels for rx, tx, error and wake-up low-pass filter wake-up function loop-back for self test operation timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels two 8-bit or one 16-bit pulse accumulators 2, 6 pwm channels programmable period and duty cycle 8-bit 2, 6-channel or 16-bit 1, 3-channel separate control for each pulse width and duty cycle center-aligned or left-aligned outputs programmable clock select logic with a wide range of frequencies fast emergency shutdown input serial interfaces two asynchronous serial communications interfaces (sci) synchronous serial peripheral interface (spi)
mc9s12h256 device user guide ?v01.20 19 inter-integrated circuit interface (iic) liquid crystal display driver with variable input voltage configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output 5 modes of operation allow for different display sizes to meet application requirements unused frontplane and backplane pins can be used as general purpose i/o 16, 24 high current drivers suited for pwm motor control each pwm channel switchable between two drivers in an h-bridge configuration left, right and center aligned outputs support for sine and cosine drive dithering output slew rate control 144-pin or 112-pin lqfp package i/o lines with 5v input and drive capability 5v a/d converter inputs operation at 32mhz equivalent to 16mhz bus speed development support single-wire background debug mode (bdm) on-chip hardware breakpoints 1.3 modes of operation user modes normal and emulation operating modes normal single-chip mode normal expanded wide mode normal expanded narrow mode emulation expanded wide mode emulation expanded narrow mode special operating modes special single-chip mode with active background debug mode special test mode ( freescale use only ) special peripheral mode ( freescale use only ) low power modes
mc9s12h256 device user guide ?v01.20 20 stop mode pseudo stop mode wait mode 1.4 block diagram figure 1-1 is a block diagram of the mc9s12h256 device.
mc9s12h256 device user guide ?v01.20 21 figure 1-1 mc9s12h256 block diagram extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor single-wire background debug module breakpoints pll xfc irq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd0 txd0 sdi/miso sdo/mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd1 txd1 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 can1 rxcan1 txcan1 pm4 pm5 pin kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ddra ddrb pta ptb ddre pte ptk ddrk ptp ddrp pts ddrs ptm ddrm ddrh pth pk2 interrupt logic fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd m0c0m m0c0p pu3 pu4 pu5 pu6 pu7 pu0 pu1 ptu ddru pwm0 m0c1m m0c1p pwm1 motor0 m1c0m m1c0p pwm2 m1c1m m1c1p pwm3 motor1 lcd sci0 can0 ph2 modb moda integration module reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 ptt ddrt fp24 fp25 fp26 fp27 pu2 m2c0m m2c0p pv3 pv4 pv5 pv6 pv7 pv0 pv1 ptv ddrv pwm4 m2c1m m2c1p pwm5 motor2 m3c0m m3c0p pwm6 m3c1m m3c1p pwm7 motor3 pv2 m4c0m m4c0p pw3 pw4 pw5 pw6 pw7 pw0 pw1 ptw ddrw pwm8 m4c1m m4c1p pwm9 motor4 m5c0m m5c0p pwm10 m5c1m m5c1p pwm11 motor5 pw2 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 vrh vrl an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa analog to digital converter ptad vrh vrl vdda vssa kwj2 kwj0 kwj1 kwj3 pj3 pj0 pj1 ddrj ptj pj2 256k bytes flash eeprom 4k bytes eeprom 12k bytes ram multiplexed address/data bus ppage data15 motor0 and motor1 supply vddm1 vssm1 motor2 and motor3 supply vddm2 vssm2 motor4 and motor5 supply vddm3 vssm3 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs/romone xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb/ t a glo r/ w vddr vdd1 vss1,vss2 voltage regulator input capture and output compare timer sda scl pm0 pm1 iic vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins driver note: not all functionality shown in this block diagram is available in all packages! pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 voltage regulator reference (atd) (pwm)
mc9s12h256 device user guide ?v01.20 22 figure 1-2 is a block diagram of the MC9S12H128 device.
mc9s12h256 device user guide ?v01.20 23 figure 1-2 MC9S12H128 block diagram extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor single-wire background debug module breakpoints pll xfc irq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd0 txd0 sdi/miso sdo/mosi ps4 ps5 ps0 ps1 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 can1 rxcan1 txcan1 pm4 pm5 ddra ddrb pta ptb ddre pte ptk ddrk ptp ddrp pts ddrs ptm ddrm pk2 fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd m0c0m m0c0p pu3 pu4 pu5 pu6 pu7 pu0 pu1 ptu ddru pwm0 m0c1m m0c1p pwm1 motor0 m1c0m m1c0p pwm2 m1c1m m1c1p pwm3 motor1 lcd sci0 can0 modb moda integration module reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 ptt ddrt fp24 fp25 fp26 fp27 pu2 m2c0m m2c0p pv3 pv4 pv5 pv6 pv7 pv0 pv1 ptv ddrv pwm4 m2c1m m2c1p pwm5 motor2 m3c0m m3c0p pwm6 m3c1m m3c1p pwm7 motor3 pv2 m4c0m m4c0p pw3 pw4 pw5 pw6 pw7 pw0 pw1 ptw ddrw pwm8 m4c1m m4c1p pwm9 motor4 m5c0m m5c0p pwm10 m5c1m m5c1p pwm11 motor5 pw2 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 vrh vrl an08 vdda vssa analog to digital converter ptad vrh vrl vdda vssa 128k bytes flash eeprom 2k bytes eeprom 6k bytes ram multiplexed address/data bus ppage data15 motor0 and motor1 supply vddm1 vssm1 motor2 and motor3 supply vddm2 vssm2 motor4 and motor5 supply vddm3 vssm3 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs/romone xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb/ t a glo r/ w vddr vdd1 vss1,vss2 voltage regulator input capture and output compare timer sda scl pm0 pm1 iic vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins driver note: not all functionality shown in this block diagram is available in all packages! voltage regulator reference (atd) (pwm)
mc9s12h256 device user guide ?v01.20 24 1.5 device memory map
mc9s12h256 device user guide ?v01.20 25
mc9s12h256 device user guide ?v01.20 26 table 1-1 and figure 1-3 show the device memory map of the mc9s12h256. table 1-1 device memory map mc9s12h256 address module size (bytes) $0000 ?$0017 core (ports a, b, e, modes, inits, test) 24 $0018 ?$0019 reserved 2 $001a ?$001b device id register (partid) 2 $001c ?$001f core (memsiz, irq, hprio) 4 $0020 ?$0027 reserved 8 $0028 ?$002f core (background debug mode) 8 $0030 ?$0033 core (ppage, port k) 4 $0034 ?$003f clock and reset generator (pll, rti, cop) 12 $0040 ?$006f standard timer module 16-bit 8 channels (tim) 48 $0070 ?$007f reserved 16 $0080 ?$00af analog to digital converter 10-bit 16 channels (atd) 48 $00b0 ?$00bf reserved 16 $00c0 ?$00c7 inter integrated circuit (iic) 8 $00c8 ?$00cf serial communications interface 0 (sci0) 8 $00d0 ?$00d7 serial communications interface 1 (sci1) 8 $00d8 ?$00df serial peripheral interface (spi) 8 $00e0 ?$00ff pulse width modulator 8-bit 6 channels (pwm) 32 $0100 ?$010f flash control registers 16 $0110 ?$011b eeprom control registers 12 $011c ?$011f reserved 4 $0120 ?$0137 liquid crystal display driver 32x4 (lcd) 24 $0140 ?$017f freescale scalable controller area network 0 (mscan0) 64 $0180 ?$01bf freescale scalable controller area network 1 (mscan1) 64 $01c0 ?$01ff motor control module (mc) 64 $0200 ?$027f port integration module (pim) 128 $0280 ?$03ff reserved 384 $0000 ?$0fff eeprom array 4096 $1000 ?$3fff ram array 12288 $4000 ?$7fff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at start 16384 $8000 ?$bfff flash eeprom page window 16384 $c000 ?$ffff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at end and 256 bytes of vector space at $ff80 ?$ffff 16384
mc9s12h256 device user guide ?v01.20 27 figure 1-3 mc9s12h256 memory map table 1-2 and figure 1-4 show the device memory map of the MC9S12H128. table 1-2 device memory map MC9S12H128 address module size (bytes) $0000 ?$0017 core (ports a, b, e, modes, inits, test) 24 $0018 ?$0019 reserved 2 $001a ?$001b device id register (partid) 2 $001c ?$001f core (memsiz, irq, hprio) 4 $0020 ?$0027 reserved 8 $0028 ?$002f core (background debug mode) 8 $0030 ?$0033 core (ppage, port k) 4 $0034 ?$003f clock and reset generator (pll, rti, cop) 12 $0040 ?$006f standard timer module 16-bit 8 channels (tim) 48 $0070 ?$007f reserved 16 $0080 ?$00af analog to digital converter 10-bit 16 channels (atd) 48 $00b0 ?$00bf reserved 16 $00c0 ?$00c7 inter integrated circuit (iic) 8 $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $ff00 ext normal single chip expanded* special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff $0000 $0fff 4k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 16k boundary 12k bytes ram alignable to top ($1000 ?$3fff) or bottom ($0000 ?$2fff) initially overlapped by register space * assuming that a ??was driven onto port k7 during reset to normal expanded mode
mc9s12h256 device user guide ?v01.20 28 $00c8 ?$00cf serial communications interface 0 (sci0) 8 $00d0 ?$00d7 reserved 8 $00d8 ?$00df serial peripheral interface (spi) 8 $00e0 ?$00ff pulse width modulator 8-bit 6 channels (pwm) 32 $0100 ?$010f flash control registers 16 $0110 ?$011b eeprom control registers 12 $011c ?$011f reserved 4 $0120 ?$0137 liquid crystal display driver 32x4 (lcd) 24 $0140 ?$017f freescale scalable controller area network 0 (mscan0) 64 $0180 ?$01bf freescale scalable controller area network 1 (mscan1) 64 $01c0 ?$01ff motor control module (mc) 64 $0200 ?$027f port integration module (pim) 128 $0280 ?$03ff reserved 384 $0000 ?$07ff eeprom array 2048 $1000 ?$3fff ram array 12288 $4000 ?$7fff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at start 16384 $8000 ?$bfff flash eeprom page window 16384 $c000 ?$ffff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at end and 256 bytes of vector space at $ff80 ?$ffff 16384 table 1-2 device memory map MC9S12H128 address module size (bytes)
mc9s12h256 device user guide ?v01.20 29 figure 1-4 MC9S12H128 memory map $0000 $ffff $c000 $8000 $4000 $0400 $0800 $2800 $ff00 ext normal single chip expanded* special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2800 $3fff $0000 $07ff 2k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 16k boundary 6k bytes ram alignable to top ($2800 ?$3fff) or bottom ($0000 ?$17ff) initially overlapped by register space * assuming that a ??was driven onto port k7 during reset to normal expanded mode
mc9s12h256 device user guide ?v01.20 30 1.5.1 detailed register map $0000 - $000f mebi map 1 of 3 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: bit 7 654321 bit 0 write: $0001 portb read: bit 7 654321 bit 0 write: $0002 ddra read: bit 7 654321 bit 0 write: $0003 ddrb read: bit 7 654321 bit 0 write: $0004 reserved read: 00000000 write: $0005 reserved read: 00000000 write: $0006 reserved read: 00000000 write: $0007 reserved read: 00000000 write: $0008 porte read: bit 7 65432 bit 1 bit 0 write: $0009 ddre read: bit 7 6543 bit 2 00 write: $000a pear read: noacce 0 pipoe neclk lstre rdwe 00 write: $000b mode read: modc modb moda 0 ivis 0 emk eme write: $000c pucr read: pupke 00 pupee 00 pupbe pupae write: $000d rdriv read: rdpk 00 rdpe 00 rdpb rdpa write: $000e ebictl read: 0000000 estr write: $000f reserved read: 00000000 write: $0010 - $0014 mmc map 1 of 4 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 initrm read: ram15 ram14 ram13 ram12 ram11 00 ramhal write: $0011 initrg read: 0 reg14 reg13 reg12 reg11 000 write: $0012 initee read: ee15 ee14 ee13 ee12 000 eeon write: $0013 misc read: 0000 exstr1 exstr0 romhm romon write: $0014 mtst0 test only read: bit 7 654321 bit 0 write:
mc9s12h256 device user guide ?v01.20 31 $0015 - $0016 int map 1 of 2 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 itcr read: 0 0 0 wrint adr3 adr2 adr1 adr0 write: $0016 itest read: inte intc inta int8 int6 int4 int2 int0 write: $0017 - $0017 mmc map 2 of 4 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 mtst1 test only read: bit 7 654321 bit 0 write: $0018 - $001b miscellaneous peripherals (device user guide, table 1-5) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 reserved read: 00000000 write: $0019 reserved read: 00000000 write: $001a partidh read: id15 id14 id13 id12 id11 id10 id9 id8 write: $001b partidl read: id7 id6 id5 id4 id3 id2 id1 id0 write: $001c - $001d mmc map 3 of 4 (core and device user guide, table 1-6) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c memsiz0 read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 write: $001d memsiz1 read: rom_sw1 rom_sw0 0000 pag_sw1 pag_sw0 write: $001e - $001e mebi map 2 of 3 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e intcr read: irqe irqen 000000 write: $001f - $001f int map 2 of 2 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001f hprio read: psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 write:
mc9s12h256 device user guide ?v01.20 32 $0020 - $0027 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 - $0027 reserved read: 00000000 write: $0028 - $002f bkp (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0028 bkpct0 read: bken bkfull bkbdm bktag 0000 write: $0029 bkpct1 read: bk0mbh bk0mbl bk1mbh bk1mbl bk0rwe bk0rw bk1rwe bk1rw write: $002a bkp0x read: 0 0 bk0v5 bk0v4 bk0v3 bk0v2 bk0v1 bk0v0 write: $002b bkp0h read: bit 15 14 13 12 11 10 9 bit 8 write: $002c bkp0l read: bit 7 654321 bit 0 write: $002d bkp1x read: 0 0 bk1v5 bk1v4 bk1v3 bk1v2 bk1v1 bk1v0 write: $002e bkp1h read: bit 15 14 13 12 11 10 9 bit 8 write: $002f bkp1l read: bit 7 654321 bit 0 write: $0030 - $0031 mmc map 4 of 4 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: 0 0 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 00000000 write: $0032 - $0033 mebi map 3 of 3 (core user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk read: bit 7 654321 bit 0 write: $0033 ddrk read: bit 7 654321 bit 0 write:
mc9s12h256 device user guide ?v01.20 33 $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0000 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg test only read: 00000000 write: $0037 crgflg read: rtif porf 0 lockif lock track scmif scm write: $0038 crgint read: rtie 00 lockie 00 scmie 0 write: $0039 clksel read: pllsel pstp syswai roawai pllwai cwai rtiwai copwai write: $003a pllctl read: cme pllon auto acq 0 pre pce scme write: $003b rtictl read: 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 000 cr2 cr1 cr0 write: $003d forbyp test only read: 00000000 write: $003e ctctl test only read: 00000000 write: $003f armcop read: 00000000 write: bit 7 654321 bit 0 $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 00000000 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 654321 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca 0000 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write:
mc9s12h256 device user guide ?v01.20 34 $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 000 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0000000 write: $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 654321 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 654321 bit 0 write: $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 654321 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 654321 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0059 tc4 (lo) read: bit 7 654321 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 654321 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 654321 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 654321 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paovi pai write: $0061 paflg read: 000000 paovf paif write: $0062 pacnt (hi) read: bit 7 654321 bit 0 write: $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 35 $0063 pacnt (lo) read: bit 7 654321 bit 0 write: $0064 reserved read: write: $0065 reserved read: write: $0066 reserved read: write: $0067 reserved read: write: $0068 reserved read: write: $0069 reserved read: write: $006a reserved read: write: $006b reserved read: write: $006c reserved read: write: $006d timtst test only read: 000000 tcbyp pcbyp write: $006e reserved read: write: $006f reserved read: write: $0070 - $007f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0070 - $007f reserved read: 00000000 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atdctl0 read: 00000000 write: $0081 atdctl1 read: 00000000 write: $0082 atdctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atdctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atdctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atdctl5 read: djm dsgn scan mult cd cc cb ca write: $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 36 $0086 atdstat0 read: scf 0 etorf fifor cc3 cc2 cc1 cc0 write: $0087 reserved read: 00000000 write: $0088 atdtest0 read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: $0089 atdtest1 read: sar1 sar0 0 0 0 rst atdclk sc write: $008a atdstat2 read: ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 write: $008b atdstat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c atddien0 read: bit 15 14 13 12 11 10 9 bit 8 write: $008d atddien1 read: bit 7 654321 bit 0 write: $008e portad0 read: bit15 14 13 12 11 10 9 bit8 write: $008f portad1 read: bit7 654321 bit 0 write: $0090 atddr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atddr0l read: bit7 654321 bit0 write: $0092 atddr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atddr1l read: bit7 654321 bit0 write: $0094 atddr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atddr2l read: bit7 654321 bit0 write: $0096 atddr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atddr3l read: bit7 654321 bit0 write: $0098 atddr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atddr4l read: bit7 654321 bit0 write: $009a atddr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atddr5l read: bit7 654321 bit0 write: $009c atddr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atddr6l read: bit7 654321 bit0 write: $009e atddr7h read: bit15 14 13 12 11 10 9 bit8 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 37 $009f atddr7l read: bit7 654321 bit0 write: $00a0 atddr8h read: bit15 14 13 12 11 10 9 bit8 write: $00a1 atddr8l read: bit7 654321 bit0 write: $00a2 atddr9h read: bit15 14 13 12 11 10 9 bit8 write: $00a3 atddr9l read: bit7 654321 bit0 write: $00a4 atddr10h read: bit15 14 13 12 11 10 9 bit8 write: $00a5 atddr10l read: bit7 654321 bit0 write: $00a6 atddr11h read: bit15 14 13 12 11 10 9 bit8 write: $00a7 atddr11l read: bit7 654321 bit0 write: $00a8 atddr12h read: bit15 14 13 12 11 10 9 bit8 write: $00a9 atddr12l read: bit7 654321 bit0 write: $00aa atddr13h read: bit15 14 13 12 11 10 9 bit8 write: $00ab atddr13l read: bit7 654321 bit0 write: $00ac atddr14h read: bit15 14 13 12 11 10 9 bit8 write: $00ad atddr14l read: bit7 654321 bit0 write: $00ae atddr15h read: bit15 14 13 12 11 10 9 bit8 write: $00af atddr15l read: bit7 654321 bit0 write: $00b0 - $00bf reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00b0 - $00bf reserved read: 00000000 write: $00c0 - $00c7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00e1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 38 $00c2 ibcr read: iben ibie ms/ sl tx/ rx txak 00 ibswai write: rsta $00c3 ibsr read: tcf iaas ibb ibal 0srw ibif rxak write: $00c4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d 0 write: $00c5 reserved read: 0 0 0 0 0 0 0 0 write: $00c6 reserved read: 00000000 write: $00c7 reserved read: 00000000 write: $00c8 - $00cf sci0 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 sci0bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 sci0bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca sci0cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00cb sci0cr2 read: tie tcie rie ilie te re rwu sbk write: $00cc sci0sr1 read: tdre tc rdrf idle or nf fe pf write: $00cd sci0sr2 read: 00000 brk13 txdir raf write: $00ce sci0drh read: r8 t8 000000 write: $00cf sci0drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 sci1 (asynchronous serial interface) only on mc9s12h256 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d0 sci1bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00d1 sci1bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00d2 sci1cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00d3 sci1cr2 read: tie tcie rie ilie te re rwu sbk write: $00d4 sci1sr1 read: tdre tc rdrf idle or nf fe pf write: $00c0 - $00c7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 39 $00d5 sci1sr2 read: 00000 brk13 txdir raf write: $00d6 sci1drh read: r8 t8 000000 write: $00d7 sci1drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d8 - $00df spi (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spicr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spicr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spibr read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spisr read: spif 0 sptef modf 0000 write: $00dc reserved read: 00000000 write: $00dd spidr read: bit7 654321 bit0 write: $00de reserved read: 00000000 write: $00df reserved read: 00000000 write: $00e0 - $00ff pwm (pulse width modulator 8 bit 6 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 pwme read: 0 0 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $00e1 pwmpol read: 0 0 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $00e2 pwmclk read: 0 0 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $00e3 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $00e4 pwmcae read: 0 0 cae5 cae4 cae3 cae2 cae1 cae0 write: $00e5 pwmctl read: 0 con45 con23 con01 pswai pfrz 00 write: $00e6 pwmtst test only read: 00000000 write: $00e7 pwmprsc test only read: 00000000 write: $00e8 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $00d0 - $00d7 sci1 (asynchronous serial interface) only on mc9s12h256 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 40 $00e9 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $00ea pwmscnta test only read: 00000000 write: $00eb pwmscntb test only read: 00000000 write: $00ec pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ed pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ee pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ef pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f0 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f1 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f2 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f3 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f4 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f5 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f6 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f7 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f8 pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f9 pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fa pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fb pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fc pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fd pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fe pwmsdn read: pwmif pwmie pwmrstrt pwmlvl 0 pwm5in pwm5inl pwm5ena write: $00ff reserved read: 00000000 write: $00e0 - $00ff pwm (pulse width modulator 8 bit 6 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 41 $0100 - $010f flash control register (fts256k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen nv6 nv5 nv4 nv3 nv2 sec1 sec0 write: $0102 reserved read: 0 0 0 wrall 000 0 write: $0103 fcnfg read: cbeie ccie keyacc 000 bksel1 bksel0 write: $0104 fprot read: fpopen nv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 write: $0105 fstat read: cbeif ccif pviol accerr 0 blank 00 write: $0106 fcmd read: 0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 write: $0107 reserved for factory test read: 00000000 write: $0108 faddrhi read: 0 bit 14 13 12 11 10 9 bit 8 write: $0109 faddrlo read: bit 7 654321 bit 0 write: $010a fdatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $010b fdatalo read: bit 7 654321 bit 0 write: $010c - $010f reserved read: 00000000 write: $0110 - $011b eeprom control register (eets4k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0110 eclkdiv read: edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 write: $0111 reserved read: 00000000 write: $0112 reserved for factory test read: 00000000 write: $0113 ecnfg read: cbeie ccie 000000 write: $0114 eprot read: epopen nv6 nv5 nv4 epdis ep2 ep1 ep0 write: $0115 estat read: cbeif ccif pviol accerr 0 blank 00 write: $0116 ecmd read: 0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 write: $0117 reserved for factory test read: 00000000 write: $0118 eaddrhi read: 00000 10 9 bit 8 write:
mc9s12h256 device user guide ?v01.20 42 $0119 eaddrlo read: bit 7 654321 bit 0 write: $011a edatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $011b edatalo read: bit 7 654321 bit 0 write: $011c - $011f reserved for ram control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $011c - $011f reserved read: 00000000 write: $0120 - $0137 lcd (liquid crystal display 32 frontplanes, 4 backplanes) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0120 lcdcr0 read: lcden 0 lclk2 lclk1 lclk0 bias duty1 duty0 write: $0121 lcdcr1 read: 000000 lcdswai lcdrpstp write: $0122 fpenr0 read: fpen7 fpen6 fpen5 fpen4 fpen3 fpen2 fpen1 fpen0 write: $0123 fpenr1 read: fpen15 fpen14 fpen13 fpen12 fpen11 fpen10 fpen9 fpen8 write: $0124 fpenr2 read: fpen23 fpen22 fpen21 fpen20 fpen19 fpen18 fpen17 fpen16 write: $0125 fpenr3 read: fpen31 fpen30 fpen29 fpen28 fpen27 fpen26 fpen25 fpen24 write: $0126 reserved read: 00000000 write: $0127 reserved read: 00000000 write: $0128 lcdram0 read: fp1bp3 fp1bp2 fp1bp1 fp1bp0 fp0bp3 fp0bp2 fp0bp1 fp0bp0 write: $0129 lcdram1 read: fp3bp3 fp3bp2 fp3bp1 fp3bp0 fp2bp3 fp2bp2 fp2bp1 fp2bp0 write: $012a lcdram2 read: fp5bp3 fp5bp2 fp5bp1 fp5bp0 fp4bp3 fp4bp2 fp4bp1 fp4bp0 write: $012b lcdram3 read: fp7bp3 fp7bp2 fp7bp1 fp7bp0 fp6bp3 fp6bp2 fp6bp1 fp6bp0 write: $012c lcdram4 read: fp9bp3 fp9bp2 fp9bp1 fp9bp0 fp8bp3 fp8bp2 fp8bp1 fp8bp0 write: $012d lcdram5 read: fp11bp3 fp11bp2 fp11bp1 fp11bp0 fp10bp3 fp10bp2 fp10bp1 fp10bp0 write: $012e lcdram6 read: fp13bp3 fp13bp2 fp13bp1 fp13bp0 fp12bp3 fp12bp2 fp12bp1 fp12bp0 write: $012f lcdram7 read: fp15bp3 fp15bp2 fp15bp1 fp15bp0 fp14bp3 fp14bp2 fp14bp1 fp14bp0 write: $0110 - $011b eeprom control register (eets4k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 43 $0130 lcdram8 read: fp17bp3 fp17bp2 fp17bp1 fp17bp0 fp16bp3 fp16bp2 fp16bp1 fp16bp0 write: $0131 lcdram9 read: fp19bp3 fp19bp2 fp19bp1 fp19bp0 fp18bp3 fp18bp2 fp18bp1 fp18bp0 write: $0132 lcdram10 read: fp21bp3 fp21bp2 fp21bp1 fp21bp0 fp20bp3 fp20bp2 fp20bp1 fp20bp0 write: $0133 lcdram11 read: fp23bp3 fp23bp2 fp23bp1 fp23bp0 fp22bp3 fp22bp2 fp22bp1 fp22bp0 write: $0134 lcdram12 read: fp25bp3 fp25bp2 fp25bp1 fp25bp0 fp24bp3 fp24bp2 fp24bp1 fp24bp0 write: $0135 lcdram13 read: fp27bp3 fp27bp2 fp27bp1 fp27bp0 fp26bp3 fp26bp2 fp26bp1 fp26bp0 write: $0136 lcdram14 read: fp29bp3 fp29bp2 fp29bp1 fp29bp0 fp28bp3 fp28bp2 fp28bp1 fp28bp0 write: $0137 lcdram15 read: fp31bp3 fp31bp2 fp31bp1 fp31bp0 fp30bp3 fp30bp2 fp30bp1 fp30bp0 write: $0140 - $017f can0 (freescale scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 can0ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 can0ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0142 can0btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 can0btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 can0rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0145 can0rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0146 can0tflg read: 00000 txe2 txe1 txe0 write: $0147 can0tier read: 00000 txeie2 txeie1 txeie0 write: $0148 can0tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0149 can0taak read: 00000abtak2abtak1abtak0 write: $014a can0tbsel read: 00000 tx2 tx1 tx0 write: $014b can0idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 00000000 write: $014d reserved read: 00000000 write: $014e can0rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $0120 - $0137 lcd (liquid crystal display 32 frontplanes, 4 backplanes) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 44 $014f can0txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0158 - $015b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f can0rxfg read: foreground receive buffer see table 1-3 write: $0170 - $017f can0txfg read: foreground transmit buffer see table 1-3 write: table 1-3 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0160 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 can0ridr0 write: $0161 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 can0ridr1 write: $0162 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: can0ridr2 write: $0163 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: can0ridr3 write: $0164- $016b can0rdsr0 - can0rdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $016c can0rdlr read: dlc3 dlc2 dlc1 dlc0 write: $016d reserved read: write: $016e can0rtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $016f can0rtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0170 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 can0tidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $0171 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 can0tidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $0140 - $017f can0 (freescale scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 45 $0172 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 can0tidr2 write: standard id read: write: $0173 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr can0tidr3 write: standard id read: write: $0174- $017b can0tdsr0 - can0tdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $017c can0tdlr read: dlc3 dlc2 dlc1 dlc0 write: $017d con0ttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $017e can0ttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $017f can0ttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $01bf can1 (freescale scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0180 can1ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0181 can1ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0182 can1btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0183 can1btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0184 can1rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0185 can1rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0186 can1tflg read: 00000 txe2 txe1 txe0 write: $0187 can1tier read: 00000 txeie2 txeie1 txeie0 write: $0188 can1tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0189 can1taak read: 00000abtak2abtak1abtak0 write: $018a can1tbsel read: 00000 tx2 tx1 tx0 write: $018b can1idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $018c reserved read: 00000000 write: $018d reserved read: 00000000 write: table 1-3 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 46 $018e can1rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $018f can1txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0190 - $0193 can1idar0 - can1idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0194 - $0197 can1idmr0 - can1idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0198 - $019b can1idar4 - can1idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019c - $019f can1idmr4 - can1idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01a0 - $01af can1rxfg read: foreground receive buffer see table 1-3 write: $01b0 - $01bf can1txfg read: foreground transmit buffer see table 1-3 write: table 1-4 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01a0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 can1ridr0 write: $01a1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 can1ridr1 write: $01a2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: can1ridr2 write: $01a3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: can1ridr3 write: $01a4- $01ab can1rdsr0 - can1rdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $01ac can1rdlr read: dlc3 dlc2 dlc1 dlc0 write: $01ad reserved read: write: $01ae can1rtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $01af can1rtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $01b0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 can1tidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $0180 - $01bf can1 (freescale scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 47 $01b1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 can1tidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $01b2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 can1tidr2 write: standard id read: write: $01b3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr can1tidr3 write: standard id read: write: $01b4- $01bb can1tdsr0 - can1tdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $01bc can1tdlr read: dlc3 dlc2 dlc1 dlc0 write: $01bd con1ttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $01be can1ttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $01bf can1ttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $01c0 - $01ff mc (motor controller 10bit 12 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01c0 mcctl0 read: 0 mcpre1 mcpre0 mcswai fast dith 0 mctoif write: $01c1 mcctl1 read: recirc 000000 mctoie write: $01c2 mcper (hi) read: 00000 p10 p9 p8 write: $01c3 mcper (lo) read: p7 p6 p5 p4 p3 p2 p1 p0 write: $01c4 reserved read: 00000000 write: $01c5 reserved read: 00000000 write: $01c6 reserved read: 00000000 write: $01c7 reserved read: 00000000 write: $01c8 reserved read: 00000000 write: $01c9 reserved read: 00000000 write: $01ca reserved read: 00000000 write: $01cb reserved read: 00000000 write: table 1-4 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 48 $01cc reserved read: 00000000 write: $01cd reserved read: 00000000 write: $01ce reserved read: 00000000 write: $01cf reserved read: 00000000 write: $01d0 mccc0 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d1 mccc1 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d2 mccc2 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d3 mccc3 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d4 mccc4 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d5 mccc5 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d6 mccc6 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d7 mccc7 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d8 mccc8 read: om1 om0 am1 am0 00 cd1 cd0 write: $01d9 mccc9 read: om1 om0 am1 am0 00 cd1 cd0 write: $01da mccc10 read: om1 om0 am1 am0 00 cd1 cd0 write: $01db mccc11 read: om1 om0 am1 am0 00 cd1 cd0 write: $01dc reserved read: 00000000 write: $01dd reserved read: 00000000 write: $01de reserved read: 00000000 write: $01df reserved read: 00000000 write: $01e0 mcdc0 (hi) read: s ssss d10 d9 d8 write: $01e1 mcdc0 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01e2 mcdc1 (hi) read: s ssss d10 d9 d8 write: $01e3 mcdc1 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01e4 mcdc2 (hi) read: s ssss d10 d9 d8 write: $01c0 - $01ff mc (motor controller 10bit 12 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 49 $01e5 mcdc2 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01e6 mcdc3 (hi) read: s ssss d10 d9 d8 write: $01e7 mcdc3 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01e8 mcdc4 (hi) read: s ssss d10 d9 d8 write: $01e9 mcdc4 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01ea mcdc5 (hi) read: s ssss d10 d9 d8 write: $01eb mcdc5 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01ec mcdc6 (hi) read: s ssss d10 d9 d8 write: $01ed mcdc6 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01ee mcdc7 (hi) read: s ssss d10 d9 d8 write: $01ef mcdc7 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01f0 mcdc8 (hi) read: s ssss d10 d9 d8 write: $01f1 mcdc8 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01f2 mcdc9 (hi) read: s ssss d10 d9 d8 write: $01f3 mcdc9 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01f4 mcdc10 (hi) read: s ssss d10 d9 d8 write: $01f5 mcdc10 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01f6 mcdc11 (hi) read: s ssss d10 d9 d8 write: $01f7 mcdc11 (lo) read: d7 d6 d5 d4 d3 d2 d1 d0 write: $01f8 reserved read: 00000000 write: $01f9 reserved read: 00000000 write: $01fa reserved read: 00000000 write: $01fb reserved read: 00000000 write: $01fc reserved read: 00000000 write: $01c0 - $01ff mc (motor controller 10bit 12 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 50 $01fd reserved read: 00000000 write: $01fe reserved read: 00000000 write: $01ff reserved read: 00000000 write: $0200 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0200 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0201 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0202 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0203 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0204 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0205 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0206 reserved read: 00000000 write: $0207 reserved read: 00000000 write: $0208 pts read: pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 write: $0209 ptis read: ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 write: $020a ddrs read: ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: $020b rdrs read: rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 write: $020c pers read: pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 write: $020d ppss read: ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 write: $020e woms read: woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 write: $020f reserved read: 00000000 write: $0210 ptm read: 0 0 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0211 ptim read: 0 0 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0212 ddrm read: 0 0 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $01c0 - $01ff mc (motor controller 10bit 12 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 51 $0213 rdrm read: 0 0 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0214 perm read: 0 0 perm5 perm4 perm3 perm2 perm1 perm0 write: $0215 ppsm read: 0 0 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0216 womm read: 0 0 womm5 womm4 womm3 womm2 womm1 womm0 write: $0217 reserved read: 00000000 write: $0218 ptp read: 0 0 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write: $0219 ptip read: 0 0 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $021a ddrp read: 0 0 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $021b rdrp read: 0 0 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $021c perp read: 0 0 perp5 perp4 perp3 perp2 perp1 perp0 write: $021d ppsp read: 0 0 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $021e reserved read: 00000000 write: $021f reserved read: 00000000 write: $0220 pth read: pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 write: $0221 ptih read: ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 write: $0222 ddrh read: ddrh7 ddrh7 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: $0223 rdrh read: rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 write: $0224 perh read: perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 write: $0225 ppsh read: ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 write: $0226 pieh read: pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 write: $0227 pifh read: pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 write: $0228 ptj read: 0000 ptj3 ptj2 ptj1 ptj0 write: $0229 ptij read: 0000 ptij3 ptij2 ptij1 ptij0 write: $022a ddrj read: 0000 ddrj3 ddrj2 ddrj1 ddrj0 write: $022b rdrj read: 0000 rdrj3 rdrj2 rdrj1 rdrj0 write: $0200 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 52 $022c perj read: 0000 perj3 perj2 perj1 perj0 write: $022d ppsj read: 0000 ppsj3 ppsj2 ppsj1 ppsj0 write: $022e piej read: 0000 piej3 piej2 piej1 piej0 write: $022f pifj read: 0000 pifj3 pifj2 pifj1 pifj0 write: $0230 ptl read: ptl7 ptl6 ptl5 ptl4 ptl3 ptl2 ptl1 ptl0 write: $0231 ptil read: ptil7 ptil6 ptil5 ptil4 ptil3 ptil2 ptil1 ptil0 write: $0232 ddrl read: ddrl7 ddrl7 ddrl5 ddrl4 ddrl3 ddrl2 ddrl1 ddrl0 write: $0233 rdrl read: rdrl7 rdrl6 rdrl5 rdrl4 rdrl3 rdrl2 rdrl1 rdrl0 write: $0234 perl read: perl7 perl6 perl5 perl4 perl3 perl2 perl1 perl0 write: $0235 ppsl read: ppsl7 ppsl6 ppsl5 ppsl4 ppsl3 ppsl2 ppsl1 ppsl0 write: $0236 reserved read: 00000000 write: $0237 reserved read: 00000000 write: $0238 ptu read: ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 write: $0239 ptiu read: ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 write: $023a ddru read: ddru7 ddru7 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 write: $023b srru read: srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 write: $023c peru read: peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 write: $023d ppsu read: ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 write: $023e reserved read: 00000000 write: $023f reserved read: 00000000 write: $0240 ptv read: ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 write: $0241 ptiv read: ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 write: $0242 ddrv read: ddrv7 ddrv7 ddrv5 ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 write: $0243 srrv read: srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 write: $0244 perv read: perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 write: $0200 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 53 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl at addresses $001a,$001b, respectively. the read-only value is a unique part id for each revision of the chip. table 1-5 shows the assigned part id numbers. $0245 ppsv read: ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 write: $0246 reserved read: 00000000 write: $0247 reserved read: 00000000 write: $0248 ptw read: ptw7 ptw6 ptw5 ptw4 ptw3 ptw2 ptw1 ptw0 write: $0249 ptiw read: ptiw7 ptiw6 ptiw5 ptiw4 ptiw3 ptiw2 ptiw1 ptiw0 write: $024a ddrw read: ddrw7 ddrw7 ddrw5 ddrw4 ddrw3 ddrw2 ddrw1 ddrw0 write: $024b srrw read: srrw7 srrw6 srrw5 srrw4 srrw3 srrw2 srrw1 srrw0 write: $024c perw read: perw7 perw6 perw5 perw4 perw3 perw2 perw1 perw0 write: $024d ppsw read: ppsw7 ppsw6 ppsw5 ppsw4 ppsw3 ppsw2 ppsw1 ppsw0 write: $024e reserved read: 00000000 write: $024f reserved read: 00000000 write: $0250 - $027f reserved read: 00000000 write: $0280 - $03ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 - $03ff reserved read: 00000000 write: table 1-5 assigned part id numbers device mask set number part id 1 mc9s12h256 0k78x $1000 mc9s12h256 1k78x $1001 $0200 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
mc9s12h256 device user guide ?v01.20 54 the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-6 shows the read-only values of these registers. refer to section module mapping and control (mmc) of hcs12 core user guide for further details. notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision table 1-6 memory size registers register name value memsiz0 $25 memsiz1 $81
mc9s12h256 device user guide ?v01.20 55 section 2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the block user guides of the individual ip blocks on the device. 2.1 device pinout the mc9s12h256 is available in a 112-pin and 144-pin quad flat pack (lqfp), the MC9S12H128 is available in a 112-pin quad flat pack (lqfp). most pins perform two or more functions, as described in the signal descriptions. figure 2-1 and figure 2-2 show the pin assignments. note: in expanded narrow modes the lower byte data is multiplexed with higher byte data through pins 64-71 on the 112-pin lqfp or through pins 111-118 on the 144-pin lqfp version.
mc9s12h256 device user guide ?v01.20 56 figure 2-1 pin assignments in 112-pin lqfp for mc9s12h256 and MC9S12H128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 mc9s12h-family 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/ ecs/romone/fp23 pe7/noacc/xclks/fp22 pe3/ lstrb/ taglo/fp21 pe2/r/ w/fp20 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6/ipipe1/modb m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 modc/ taghi/ bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 moda/ipip0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1
mc9s12h256 device user guide ?v01.20 57 figure 2-2 pin assignments in 144-pin lqfp for mc9s12h256 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 kwh0/ph0 kwh1/ph1 kwh2/ph2 kwh3/ph3 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 kwh4/ph4 kwh5/ph5 kwh6/ph6 kwh7/ph7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 pwm2/pp2 pwm3/pp3 pwm4/pp4 pwm5/pp5 rxd0/ps0 txd0/ps1 rxd1/ps2 txd1/ps3 vss2 vddr vddx2 vssx2 modc/ taghi/bkgd reset vddpll xfc vsspll extal xtal test sda/pm0 scl/pm1 rxcan0/pm2 txcan0/pm3 rxcan1pm4 txcan1/pm5 moda/ipipe0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6/ipipe1/modb pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 pj3/kwj3 pj2/kwj2 pj1/kwj1 pj0/kwj0 vssx1 vddx1 pk7/ ecs/romone/fp23 pe7/noacc/xclks/fp22 pe3/ lstrb/ t a glo/fp21 pe2/r/ w/fp20 pl7/fp31 pl6/fp30 pl5/fp29 pl4/fp28 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 mc9s12h-family 144 lqfp pins shown in bold are not available in the 112 lqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
mc9s12h256 device user guide ?v01.20 58 2.2 signal properties summary table 2-1 summarizes all pin functions. note: bold entries determine pins not available on 112-pin lqfp. table 2-1 signal properties pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state extal vddpll none none oscillator pins xtal vddpll reset vddx2 external reset pin test vddx2 test input xfc vddpll pll loop filter bkgd t a ghi modc vddx2 always up up background debug, tag high, mode pin pad[7:0] an[7:0] vdda none none port ad inputs, analog inputs (atd) pad[15:8] an[15:8] vdda port ad inputs, analog inputs (atd) pa[7:0] fp[15:8] addr[15:8]/ data[15:8] vddx1 pucr/ pupae down port a i/o, multiplexed address/data pb[7:0] fp[7:0] addr[7:0]/ data[7:0] vddx1 pucr/ pupbe down port b i/o, multiplexed address/data pe7 fp22 xclks noacc vddx1 pucr/ pupee down port e i/o, access, clock select, lcd driver pe6 ipipe1 modb vddx2 while reset pin is low: down port e i/o, pipe status, mode input pe5 ipipe0 moda vddx2 port e i/o, pipe status, mode input pe4 eclk vddx2 pucr/ pupee mode de- pendent port e i/o, bus clock output pe3 fp21 lstrb t a glo vddx1 port e i/o, lcd driver, byte strobe, tag low pe2 fp20 r/ w vddx1 port e i/o, r/ w in expanded modes pe1 irq vddx2 up port e input, maskable interrupt pe0 xirq vddx2 port e input, non maskable interrupt ph[7:0] kwh[7:0] vddm perh/ ppsh disabled port h i/o, interrupts pj[3:0] kwj[3:0] vddx1 perj/ ppsj disabled port j i/o, interrupts pk7 fp23 ecs romone vddx1 pucr/ pupke down port k i/o, emulation chip select, rom on enable pk[3:0] bp[3:0] xaddr[17:14] vddx1 port k i/o, lcd driver, extended addresses pl[3:0] fp[19:16] vddx1 perl/ ppsl down port l i/o, lcd drivers pl[7:4] fp[31:28] vddx1 port l i/o, lcd drivers
mc9s12h256 device user guide ?v01.20 59 pm5 txcan1 vddx2 perm/ ppsm disabled port m i/o, tx of can1 pm4 rxcan1 vddx2 port m i/o, rx of can1 pm3 txcan0 vddx2 port m i/o, tx of can0 pm2 rxcan0 vddx2 port m i/o, rx of can0 pm1 scl vddx2 port m i/o, scl of iic pm0 sda vddx2 port m i/o, sda of iic pp[5:2] pwm[5:2] vddx2 perp/ ppsp disabled port p i/o, pwm channels pp[1:0] pwm[1:0] vddx2 port p i/o, pwm channels ps7 ss vddx2 pers/ ppss disabled port s i/o, ss of spi ps6 sck vddx2 port s i/o, sck of spi ps5 mosi vddx2 port s i/o, mosi of spi ps4 miso vddx2 port s i/o, miso of spi ps3 txd1 vddx2 port s i/o, txd of sci1 ps2 rxd1 vddx2 port s i/o, rxd of sci1 ps1 txd0 vddx2 port s i/o, txd of sci0 ps0 rxd0 vddx2 port s i/o, rxd of sci0 pt[7:4] ioc[7:4] vddx1 pert/ ppst down port t i/o, timer channels pt[3:0] ioc[3:0] fp[27:24] vddx1 port t i/o, timer channels, lcd driver pu[3:0] m0c0m m0c0p m0c1m m0c1p vddm peru/ ppsu disabled port u i/o, motor0 of mc pu[7:4] m1c0m m1c0p m1c1m m1c1p vddm port u i/o, motor1 of mc pv[3:0] m2c0m m2c0p m2c1m m2c1p vddm perv/ ppsv disabled port v i/o, motor2 of mc pv[7:4] m3c0m m3c0p m3c1m m3c1p vddm port v i/o, motor3 of mc pw[3:0] m4c0m m4c0p m4c1m m4c1p vddm perw/ ppsw disabled port w i/o, motor4 of mc pw[7:4] m5c0m m5c0p, m5c1m m5c1p vddm port w i/o, motor5 of mc pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state
mc9s12h256 device user guide ?v01.20 60 2.3 detailed signal descriptions 2.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset ?external reset pin an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. 2.3.3 test ?test pin this pin is reserved for test. note: the test pin must be tied to vss in all applications. 2.3.4 xfc ?pll loop filter pin dedicated pin used to create the pll loop filter. 2.3.5 bkgd / taghi / modc background debug, tag high, and mode pin the bkgd/ taghi/modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. 2.3.6 pad[15:8] / an[15:8] ?port ad input pins [15:8] pad15-pad8 are general purpose input pins and analog inputs for the analog to digital converter. note: these pins are not available in the 112-pin lqfp version. 2.3.7 pad[7:0] / an[7:0] ?port ad input pins [7:0] pad7-pad0 are general purpose input pins and analog inputs for the analog to digital converter. 2.3.8 pa[7:0] / fp[15:8] / addr[15:8] / data[15:8] ?port a i/o pins pa7-pa0 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp15-fp8 of the lcd. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus.
mc9s12h256 device user guide ?v01.20 61 2.3.9 pb[7:0] / fp[7:0] / addr[7:0] / data[7:0] ?port b i/o pins pb7-pb0 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp7-fp0 of the lcd. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.10 pe7 / fp22 / xclks / noacc ?port e i/o pin 7 pe7 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp22 of the lcd module. the xclks signal selects between an external clock or oscillator configuration during reset. the xclks input selects between an external clock or oscillator configuration. the state of this pin is latched at the rising edge of reset. if the input is a logic high the extal pin is configured for an external clock drive. if input is a logic low an oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on extal and xtal. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or ?ree?cycle. this signal will assert when the cpu is not using the bus. 2.3.11 pe6 / modb / ipipe1 ?port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe1. this pin is an input with a pull-down device which is only active when reset is low. 2.3.12 pe5 / moda / ipipe0 ?port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe0. this pin is an input with a pull-down device which is only active when reset is low. 2.3.13 pe4 / eclk ?port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. 2.3.14 pe3 / fp21 / lstrb / taglo ?port e i/o pin 3 pe3 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp21 of the lcd module. in mcu expanded modes of operation, lstrb is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the instruction word being read into the instruction queue.
mc9s12h256 device user guide ?v01.20 62 2.3.15 pe2 / fp20 / r/ w port e i/o pin 2 pe2 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp20 of the lcd module. in mcu expanded modes of operations, this pin performs the read/write output signal for the external bus. it indicates the direction of data on the external bus. 2.3.16 pe1 / irq ?port e input pin 1 pe1 is a general purpose input pin and also the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.17 pe0 / xirq ?port e input pin 0 pe0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.18 ph[7:0] / kwh[7:0] ?port h i/o pins [7:0] ph7-ph0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. note: these pins are not available in the 112-pin lqfp version. 2.3.19 pj[3:0] / kwj[3:0] ?port j i/o pins [3:0] pj3-pj0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode.and are shared with the interrupt function. note: these pins are not available in the 112-pin lqfp version. 2.3.20 pk7 / fp23 / ecs / romone ?port k i/o pin 7 pk7 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp23 of the lcd module. during mcu expanded modes of operation, this pin is used as the emulation chip select signal ( ecs). during reset of the mcu to normal expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romone). at the rising edge of reset, the state of this pin is latched to the romon bit. 2.3.21 pk[3:0] / bp[3:0] / xaddr[17:14] ?port k i/o pins [3:0] pk3-pk0 are general purpose input or output pins. they can be configured as backplane segment driver outputs bp3-bp0 of the lcd module. in mcu expanded modes of operation, these pins provide the expanded address xaddr[17:14] for the external bus.
mc9s12h256 device user guide ?v01.20 63 2.3.22 freescalepl[7:4] / fp[31:28] ?port l i/o pins [7:4] pl7-pl4 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp31-fp28 of the lcd module. note: these pins are not available in the 112-pin lqfp version. 2.3.23 pl[3:0] / fp[19:16] ?port l i/o pins [3:0] pl3-pl0 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp19-fp16 of the lcd module. 2.3.24 pm5 / txcan1 ?port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the transmit pin txcan1 of the freescale scalable controller area network controller 1 (can1) 2.3.25 pm4 / rxcan1 ?port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the receive pin rxcan1 of the freescale scalable controller area network controller 1 (can1) 2.3.26 pm3 / txcan0 ?port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the transmit pin txcan0 of the freescale scalable controller area network controller 0 (can0) 2.3.27 pm2 / rxcan0 ?port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the receive pin rxcan0 of the freescale scalable controller area network controller 0 (can0) 2.3.28 pm1 / scl ?port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the serial clock pin scl of the inter-ic bus interface (iic). note: this pin is not available in the 112-pin lqfp version. 2.3.29 pm0 / sda ?port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the serial data pin sda of the inter-ic bus interface (iic). note: this pin is not available in the 112-pin lqfp version.
mc9s12h256 device user guide ?v01.20 64 2.3.30 pp[5:2] / pwm[5:2] port p i/o pins [5:2] pp5-pp2 are general purpose input or output pins. they can be configured as pulse width modulator (pwm) channel outputs pwm5-pwm2. note: these pins are not available in the 112-pin lqfp version. 2.3.31 pp[1:0] / pwm[1:0] port p i/o pins [1:0] pp1-pp0 are general purpose input or output pins. they can be configured as pulse width modulator (pwm) channel outputs pwm1-pwm0. 2.3.32 ps7 / ss ?port s i/o pin 7 ps7 is a general purpose input or output pin. it can be configured as slave select pin ss of the serial peripheral interface (spi). 2.3.33 ps6 / sck ?port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as serial clock pin sck of the serial peripheral interface (spi). 2.3.34 ps5 / mosi ?port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as the master output (during master mode) or slave input (during slave mode) pin mosi of the serial peripheral interface (spi). 2.3.35 ps4 / miso ?port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso for the serial peripheral interface (spi). 2.3.36 ps3 / txd1 ?port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as transmit pin txd1 of the serial communication interface 1 (sci1). note: this pin is not available in the 112-pin lqfp version. 2.3.37 ps2 / rxd1 ?port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as receive pin rxd1 of the serial communication interface 1 (sci1). note: this pin is not available in the 112-pin lqfp version.
mc9s12h256 device user guide ?v01.20 65 2.3.38 ps1 / txd0 ?port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as transmit pin txd0 of the serial communication interface 0 (sci0). 2.3.39 ps0 / rxd0 ?port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as receive pin rxd0 of the serial communication interface 0 (sci0). 2.3.40 pt[7:4] / ioc[7:4] ?port t i/o pins [7:4] pt7-pt4 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc4 of the timer (tim). 2.3.41 pt[3:0] / ioc[3:0] / fp[27:24] ?port t i/o pins [3:0] pt3-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc3-ioc0 of the timer (tim). they can be configured as frontplane segment driver outputs fp27-fp24 of the lcd module. 2.3.42 pu[7:4] / m1c1p, m1c1m, m1c0p, m1c0m ?port u i/o pins [7:4] pu7-pu4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state. 2.3.43 pu[3:0] / m0c1p, m0c1m, m0c0p, m0c0m ?port u i/o pins [3:0] pu3-pu0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state. 2.3.44 pv[7:4] / m3c1p, m3c1m, m3c0p, m3c0m ?port v i/o pins [7:4] pv7-pv4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state.
mc9s12h256 device user guide ?v01.20 66 2.3.45 pv[3:0] / m2c1p, m2c1m, m2c0p, m2c0m ?port v i/o pins [3:0] pv3-pv0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current flow through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state. 2.3.46 pw[7:4] / m5c1p, m5c1m, m5c0p, m5c0m ?port w i/o pins [7:4] pw7-pw4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive current flow through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state. 2.3.47 pw[3:0] / m4c1p, m4c1m, m4c0p, m4c0m ?port w i/o pins [3:0] pw3-pw0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive current flow through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state. 2.4 power supply pins mc9s12h256 power and ground pins are described below. note: all vss pins must be connected together in the application ( 21.2 recommended pcb layout ). because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded ( table 21-1 ). 2.4.1 vddr ?external power pin vddr is the power supply pin for the internal voltage regulator. 2.4.2 vddx1, vddx2, vssx1, vssx2 ?external power and ground pins vddx1, vddx2, vssx1 and vssx2 are the power supply and ground pins for input/output drivers.vddx1 and vddx2 as well as vssx1 and vssx2 are not internally connected.
mc9s12h256 device user guide ?v01.20 67 2.4.3 vdd1, vss1, vss2 ?core power pins vdd1, vss1 and vss2 are the core power and ground pins and related to the voltage regulator output. these pins serve as connection points for filter capacitors. vss1 and vss2 are internally connected. note: no load allowed except for bypass capacitors. 2.4.4 vdda, vssa ?power supply pins for atd and vreg vdda, vssa are the power supply and ground pins for the voltage regulator and the analog to digital converter. 2.4.5 vddm1, vddm2, vddm3 ?power supply pins for motor 0 to 5 vddm1, vddm2 and vddm3 are the supply pins for the ports u,v and w. vddm1, vddm2 and vddm3 are internally connected. 2.4.6 vssm1, vssm2, vssm3 ?ground pins for motor 0 to 5 vssm1, vssm2 and vssm3 are the ground pins for the ports u,v and w. vssm1, vssm2 and vssm3 are internally connected. 2.4.7 vlcd ?power supply reference pin for lcd driver vlcd is the voltage reference pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. 2.4.8 vrh, vrl ?atd reference voltage input pins vrh and vrl are the voltage reference pins for the analog to digital converter. 2.4.9 vddpll, vsspll ?power supply pins for pll vddpll and vsspll are the pll supply pins and serve as connection points for external loop filter components. note: no load allowed except for bypass capacitors.
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mc9s12h256 device user guide ?v01.20 69 section 3 system clock description 3.1 overview the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections crg bus clock core clock extal xtal oscillator clock s12_core iic ram sci0, sci1 pwm atd eeprom flash tim mc spi can0, can1 pim lcd
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mc9s12h256 device user guide ?v01.20 71 section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12h256. each mode has an associated default memory map and external bus configuration. three low power modes exist for the device. 4.2 modes of operation the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset ( table 4-1 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. there are two basic types of operating modes: 1. normal modes: some registers and bits are protected against accidental changes. 2. special modes: allow greater access to protected control registers and bits for special purposes such as testing. a system development and debug feature, background debug mode (bdm), is available in all modes. in special single-chip mode, bdm is active immediately after reset. some aspects of port e are not mode dependent. bit 1 of port e is a general purpose input or the irq interrupt input. irq can be enabled by bits in the cpu? condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. bit 0 of port e is a general purpose input or the xirq interrupt input. xirq can be enabled by bits in the cpu? condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. the estr bit in the ebictl register is set to one by reset in any user mode. this assures that the reset vector can be fetched table 4-1 mode selection modc modb moda mode description 000 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 0 0 1 emulation expanded narrow, bdm allowed 0 1 0 special test (expanded wide) ( freescale use only ), bdm allowed 0 1 1 emulation expanded wide, bdm allowed 1 0 0 normal single chip, bdm allowed 1 0 1 normal expanded narrow, bdm allowed 110 peripheral ( freescale use only ); bdm allowed but bus operations would cause bus con?cts (must not be used) 1 1 1 normal expanded wide, bdm allowed
mc9s12h256 device user guide ?v01.20 72 even if it is located in an external slow memory device. the pe6/modb/ipipe1 and pe5/moda/ipipe0 pins act as high-impedance mode select inputs during reset. the following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. 4.2.1 normal operating modes these modes provide three operating configurations. background debug is available in all three modes, but must first be enabled for some operations by means of a bdm background command, then activated. 4.2.1.1 normal single-chip mode there is no external expansion bus in this mode. all pins of ports a, b and e are configured as general purpose i/o pins port e bits 1 and 0 are available as general purpose input only pins with internal pull-ups enabled. all other pins of port e are bidirectional i/o pins that are initially configured as high-impedance inputs with internal pull-ups enabled. ports a and b are configured as high-impedance inputs with their internal pull-ups disabled. the pins associated with port e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb, and r/ w while the mcu is in single chip modes. in single chip modes, the associated control bits pipoe, lstre, and rdwe are reset to zero. writing the opposite state into them in single chip mode does not change the operation of the associated port e pins. in normal single chip mode, the mode register is writable one time. this allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. typically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.1.2 normal expanded wide mode in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e bit 4 is configured as the e clock output signal. these signals allow external memory and peripheral devices to be interfaced to the mcu. port e pins other than pe4/eclk are configured as general purpose i/o pins (initially high-impedance inputs with internal pull-up resistors enabled). control bits pipoe, neclk, lstre, and rdwe in the pear register can be used to configure port e pins to act as bus control outputs instead of general purpose i/o pins. it is possible to enable the pipe status signals on port e bits 6 and 5 by setting the pipoe bit in pear, but it would be unusual to do so in this mode. development systems where pipe status signals are monitored would typically use the special variation of this mode. the port e bit 2 pin can be reconfigured as the r/ w bus control signal by writing ? to the rdwe bit in pear. if the expanded system includes external devices that can be written, such as ram, the rdwe bit
mc9s12h256 device user guide ?v01.20 73 would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. the port e bit 3 pin can be reconfigured as the lstrb bus control signal by writing ??to the lstre bit in pear. the default condition of this pin is a general purpose input because the lstrb function is not needed in all expanded wide applications. the port e bit 4 pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. the e clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 4.2.1.3 normal expanded narrow mode this mode is used for lower cost production systems that use 8-bit wide external eproms or rams. such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. ports a and b are configured as a 16-bit address bus and port a is multiplexed with data. internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. since the pear register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. the pe3/ lstrb pin is always a general purpose i/o pin in normal expanded narrow mode. although it is possible to write the lstre bit in pear to ? in this mode, the state of lstre is overridden and port e bit 3 cannot be reconfigured as the lstrb output. it is possible to enable the pipe status signals on port e bits 6 and 5 by setting the pipoe bit in pear, but it would be unusual to do so in this mode. lstrb would also be needed to fully understand system activity. development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. the pe4/eclk pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. in normal expanded narrow mode, the e clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. the pe2/r/w pin is initially configured as a general purpose input with a pull-up but this pin can be reconfigured as the r/ w bus control signal by writing ??to the rdwe bit in pear. if the expanded narrow system includes external devices that can be written such as ram, the rdwe bit would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. 4.2.1.4 internal visibility internal visibility is available when the mcu is operating in expanded wide modes or special narrow mode. it is not available in single-chip, peripheral or normal expanded narrow modes. internal visibility is enabled by setting the ivis bit in the mode register.
mc9s12h256 device user guide ?v01.20 74 if an internal access is made while e, r/ w, and lstrb are configured as bus control outputs and internal visibility is off (ivis=0), e will remain low for the cycle, r/ w will remain high, and address, data and the lstrb pins will remain at their previous state. when internal visibility is enabled (ivis=1), certain internal cycles will be blocked from going external. during cycles when the bdm is selected, r/ w will remain high, data will maintain its previous state, and address and lstrb pins will be updated with the internal value. during cpu no access cycles when the bdm is not driving, r/ w will remain high, and address, data and the lstrb pins will remain at their previous state. 4.2.1.5 emulation expanded wide mode in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals. these signals allow external memory and peripheral devices to be interfaced to the mcu. these signals can also be used by a logic analyzer to monitor the progress of application programs. the bus control related pins in port e (pe7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/ lstrb/ taglo, and pe2/r/ w) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in special mode are restricted. 4.2.1.6 emulation expanded narrow mode expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. accesses to internal resources that have been mapped external (i.e. porta, portb, ddra, ddrb, porte, ddre, pear, pucr, rdriv) will be accessed with a 16-bit data bus on ports a and b. accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using port a as an 8-bit data bus. internal operations continue to use full 16-bit data paths. they are only visible externally as 16-bit information if ivis=1. ports a and b are configured as multiplexed address and data output ports. during external accesses, address a15, data d15 and d7 are associated with pa7, address a0 is associated with pb0 and data d8 and d0 are associated with pa0. during internal visible accesses and accesses to internal resources that have been mapped external, address a15 and data d15 is associated with pa7 and address a0 and data d0 is associated with pb0. the bus control related pins in port e (pe7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/ lstrb/ taglo, and pe2/r/ w) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in special mode are restricted. 4.2.2 special operating modes there are two special operating modes that correspond to normal operating modes. these operating modes are commonly used in factory testing and system development.
mc9s12h256 device user guide ?v01.20 75 4.2.2.1 special single-chip mode when the mcu is reset in this mode, the background debug mode is enabled and active. the mcu does not fetch the reset vector and execute application code as it would in other modes. instead the active background mode is in control of cpu execution and bdm firmware is waiting for additional serial commands through the bkgd pin. when a serial command instructs the mcu to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the mcu was reset. there is no external expansion bus after reset in this mode. ports a and b are initially simple bidirectional i/o pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to the mode select bits in the mode register (which is allowed in special modes) can change this after reset. all of the port e pins (except pe4/eclk) are initially configured as general purpose high-impedance inputs with pull-ups enabled. pe4/eclk is configured as the e clock output in this mode. the pins associated with port e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb, and r/ w while the mcu is in single chip modes. in single chip modes, the associated control bits pipoe, lstre and rdwe are reset to zero. writing the opposite value into these bits in single chip mode does not change the operation of the associated port e pins. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. typically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.2.2 special test mode (freescale use only) in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals. in special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. 4.2.3 test operating mode (freescale use only) there is a test operating mode in which an external master, such as an i.c. tester, can control the on-chip peripherals. 4.2.3.1 peripheral mode this mode is intended for freescale factory testing of the mcu. in this mode, the cpu is inactive and an external (tester) bus master drives address, data and bus control signals in through ports a, b and e. in effect, the whole mcu acts as if it was a peripheral under control of an external cpu. this allows faster testing of on-chip memory and peripherals than previous testing methods. since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the mcu into a different mode. background debugging should not be used while the mcu is in special peripheral mode as internal bus conflicts between bdm and the external master can cause improper operation of both functions.
mc9s12h256 device user guide ?v01.20 76 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: protection of the contents of flash, protection of the contents of eeprom, operation in single-chip mode, operation from external memory with internal flash and eeprom disabled. the user must be reminded that part of the security must lie with the user? code. an extreme example would be user? code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the user? program. an example of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters stored in eeprom. 4.3.1 securing the microcontroller once the user has programmed the flash and eeprom (if desired), the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block user guide for more details on the security configuration. 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash and eeprom will be disabled. bdm operations will be blocked. 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash and eeprom must be erased. this can be done through an external program in expanded mode. once the user has erased the flash and eeprom, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash and eeprom. once this program
mc9s12h256 device user guide ?v01.20 77 completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes consult the respective block user guide for information on the module behavior in stop, pseudo stop, and wait mode.
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mc9s12h256 device user guide ?v01.20 79 section 5 resets and interrupts 5.1 overview consult the exception processing section of the hcs12 core user guide for information on resets and interrupts. 5.2 vectors 5.2.1 vector table table 5-1 lists interrupt sources and vectors in default order of priority. table 5-1 reset and interrupt vector table vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff external or power on reset none none - $fffc, $fffd clock monitor fail reset none copctl (cme, fcme) - $fffa, $fffb cop failure reset none cop rate select - $fff8, $fff9 unimplemented instruction trap none none - $fff6, $fff7 swi none none - $fff4, $fff5 xirq x-bit none - $fff2, $fff3 irq i-bit intcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit rtictl (rtie) $f0 $ffee, $ffef timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf timer over?w i-bit tscr2 (toi) $de $ffdc, $ffdd pulse accumulator a over?w i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi i-bit spicr1 (spie) $d8 $ffd6, $ffd7 sci0 i-bit sc0cr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci1 i-bit sc1cr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd i-bit atdctl2 (ascie) $d2 $ffd0, $ffd1 reserved $ffce, $ffcf port j i-bit ptjif (ptjie) $ce $ffcc, $ffcd port h i-bit pthif (pthie) $cc $ffca, $ffcb reserved
mc9s12h256 device user guide ?v01.20 80 5.3 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block user guides for register reset states. 5.3.1 i/o pins refer to the hcs12 core user guides for mode dependent pin configuration of port a, b, e and k out of reset. refer to the pim block user guide for reset configurations of all peripheral module ports. note: for devices assembled in 112-pin lqfp packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. $ffc8, $ffc9 reserved $ffc6, $ffc7 crg pll lock i-bit crgint (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit crgint (scmie) $c4 $ffc2, $ffc3 reserved $ffc0, $ffc1 iic bus i-bit ibcr (ibie) $c0 $ffbe, $ffbf reserved $ffbc, $ffbd reserved $ffba, $ffbb eeprom i-bit eectl (ccie, cbeie) $ba $ffb8, $ffb9 flash i-bit fctl (ccie, cbeie) $b8 $ffb6, $ffb7 can0 wake-up i-bit can0rier (wupie) $b6 $ffb4, $ffb5 can0 errors i-bit can0rier (cscie, ovrie) $b4 $ffb2, $ffb3 can0 receive i-bit can0rier (rxfie) $b2 $ffb0, $ffb1 can0 transmit i-bit can0tier (txeie[2:0]) $b0 $ffae, $ffaf can1 wake-up i-bit can0rier (wupie) $ae $ffac, $ffad can1 errors i-bit can1rier (cscie, ovrie) $ac $ffaa, $ffab can1 receive i-bit can1rier (rxfie) $aa $ffa8, $ffa9 can1 transmit i-bit can1tier (txeie[2:0]) $a8 $ff98 to $ffa7 reserved $ff96, $ff97 motor control timer over?w i-bit mcctl1 (mcocie) $96 $ff9e to $ff95 reserved $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn(pwmie) $8c $ff80 to $ff8b reserved table 5-1 reset and interrupt vector table vector address interrupt source ccr mask local enable hprio value to elevate
mc9s12h256 device user guide ?v01.20 81 5.3.2 memory refer to table 1-1 for locations of the memories depending on the operating mode after reset the ram array is not automatically initialized out of reset.
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mc9s12h256 device user guide ?v01.20 83 section 6 hcs12 core block description consult the hcs12 core user guide for information about the hcs12 core modules, i.e. central processing unit (cpu), interrupt module (int), module mapping control module (mmc), multiplexed external bus interface (mebi), breakpoint module (bkp) and background debug mode module (bdm). section 7 clock and reset generator (crg) block description consult the crg block user guide for information about the clock and reset generator module. 7.1 device-specific information 7.1.1 xclks the xclks input signal is active high (see 2.3.10 pe7 / fp22 / xclks / noacc port e i/o pin 7 ). section 8 timer (tim) block description consult the tim_16b8c block user guide for information about the timer module. section 9 analog to digital converter (atd) block description consult the atd_10b16c block user guide for information about the analog to digital converter module. section 10 inter-ic bus (iic) block description consult the iic block user guide for information about the inter-ic bus module. section 11 serial communications interface (sci) block description
mc9s12h256 device user guide ?v01.20 84 there are two serial communications interfaces (sci0 and sci1) implemented on the mc9s12h256 device and one sci (sci0) on MC9S12H128. consult the sci block user guide for information about each serial communications interface module. section 12 serial peripheral interface (spi) block description consult the spi block user guide for information about the serial peripheral interface module. section 13 pulse width modulator (pwm) block description consult the pwm_8b6c block user guide for information about the pulse width modulator module. section 14 flash eeprom 256k block description consult the fts256k block user guide for information about the flash module. section 15 eeprom 4k block description consult the eets4k block user guide for information about the eeprom module. section 16 ram block description the ram module does not contain any control registers. thus no block user guide is available. this module supports single-cycle misaligned word accesses without wait states. section 17 liquid crystal display driver (lcd) block description consult the lcd_32f4b block user guide for information about the liquid crystal display driver module. section 18 mscan block description
mc9s12h256 device user guide ?v01.20 85 there are two mscan modules (can0 and can1) implemented on the mc9s12h256 device. consult the mscan block user guide for information on each mscan. section 19 pwm motor control (mc) block description consult the mc_10b12c block user guide for information about the pwm motor control module. section 20 port integration module (pim) block description consult the pim_9h256 block user guide for information about the port integration module. section 21 voltage regulator (vreg) block description consult the vreg block user guide for information about the dual output linear voltage regulator. 21.1 device-specific information 21.1.1 vregen there is no vregen pin implemented on this device. 21.1.2 modes of operation 21.1.2.1 run mode vreg enters run mode whenever the cpu is neither in stop nor in pseudo stop mode. both regulating loops operate in run mode with full performance. 21.1.2.2 standby mode vreg enters standby mode when the cpu operates either in stop or in pseudo stop mode. the supply of the core logic as well as the oscillators are derived from two voltage clamps. standby mode minimizes quiescent current drawn by the voltage regulator block. 21.1.2.3 shutdown mode vreg shutdown mode is not available on mc9s12h family devices.
mc9s12h256 device user guide ?v01.20 86 21.2 recommended pcb layout figure 21-1 lqfp112 recommended pcb layout c9 c4 c6 c8 c2 c1 c10 c11 q1 c13 c12 r1 vssx1 vddx1 vddr/ vddm2 vssm2 vdd1 vss1 vddpll vsspll vdda vssa c3 c7 vddm1 vssm1 vddx2 c5 vddm3 vssm3 c14
mc9s12h256 device user guide ?v01.20 87 figure 21-2 lqfp144 recommended pcb layout c8 vssx1 vddx1 c6 vddm2 vssm2 c7 vddm1 vssm1 c5 vddm3 vssm3 c9 c4 c10 c11 q1 c13 c12 r1 vddr/ vddpll vsspll c3 vddx2 c2 c1 vdd1 vss1 vdda vssa c14
mc9s12h256 device user guide ?v01.20 88 the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible to the corresponding pins(c1 ?c9). central point of the ground star should be the vss1 pin. use low ohmic low inductance connections between vss1, vss2, vssa, vssx1,2 and vssm1,2,3. vsspll must be directly connected to vss1. keep traces of vsspll, extal and xtal as short as possible and occupied board area for c10, c11, c14 and q1 as small as possible. do not place other signals or supplies underneath area occupied by c10, c11, c14 and q1 and the connection area to the mcu. central power input should be fed in at the vdda/vssa pins. table 21-1 recommended components component purpose type value c1 vdd1 ?ter cap ceramic x7r 100 .. 220nf c2 vdda ?ter cap x7r/tantalum >=100nf c3 vddx2 ?ter cap x7r/tantalum >=100nf c4 vddr ?ter cap x7r/tantalum >=100nf c5 vddm3 ?ter cap x7r/tantalum >=100nf c6 vddm2 ?ter cap x7r/tantalum >=100nf c7 vddm1 ?ter cap x7r/tantalum >=100nf c8 vddx1 ?ter cap x7r/tantalum >=100nf c9 vddpll ?ter cap ceramic x7r 100nf .. 220nf c10 osc load cap see crg block user guide c11 osc load cap c12 pll loop ?ter cap c13 pll loop ?ter cap c14 dc cutoff cap r1 pll loop ?ter res q1 quartz/resonator
mc9s12h256 device user guide ?v01.20 89 appendix a electrical characteristics a.1 general this supplement contains the most accurate electrical information for the mc9s12h256 and MC9S12H128 microcontroller available at the time of publication. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification is shown in the column labeled ??in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12h256 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator and pll as well as the digital core. the vdda, vssa pair supplies the a/d converter and the resistor ladder of the internal voltage regulator. the vddx1/vssx1 and vddx2/vssx2 pairs supply the i/o pins except ph, pu, pv and pw. vddr supplies the internal voltage regulator. vddm1/vssm1, vddm2/vssm2 and vddm3/vssm3 pairs supply the ports ph, pu, pv and pw.
mc9s12h256 device user guide ?v01.20 90 vdd1, vss1 and vss2 are the supply pins for the digital logic, vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdda, vddx1, vddx2, vddm as well as vssa, vssx1, vssx2 and vssm are connected by anti-parallel diodes for esd protection. note: in the following context vdd5 is used for either vdda, vddm, vddr and vddx1/2; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx1/2, vddm and vddr pins. vdd is used for vdd1 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vddpll. a.1.3 pins there are four groups of functional pins. a.1.3.1 5v i/o pins those i/o pins have a nominal level of 5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group is made up by the vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. ensure external vdd5 load will shunt current greater than maximum injection current. this will be the
mc9s12h256 device user guide ?v01.20 91 greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1 absolute maximum ratings 1 notes : 1. beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 ?.3 6.0 v 2 digital logic supply voltage 2 2. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd ?.3 3.0 v 3 pll supply voltage 2 v ddpll ?.3 3.0 v 4 voltage difference vddx1 to vddx2 to vddm and vdda ? vddx ?.3 0.3 v 5 voltage difference vssx to vssr and vssa ? vssx ?.3 0.3 v 6 digital i/o input voltage v in ?.3 6.0 v 7 analog reference v rh, v rl ?.3 6.0 v 8 xfc, extal, xtal inputs v ilv ?.3 3.0 v 9 test input v test ?.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins except pu, pv and pw 3 3. all digital i/o pins are internally clamped to v ssx1/2 and v ddx1/2 , v ssm and v ddm or v ssa and v dda . i d ?5 +25 ma 11 instantaneous maximum current single pin limit for port pu, pv and pw 4 4. ports pu, pv, pw are internally clamped to v ssm and v ddm . i d ?5 +55 ma 12 instantaneous maximum current single pin limit for xfc, extal, xtal 5 i dl ?5 +25 ma 13 instantaneous maximum current single pin limit for test 6 i dt ?.25 0 ma 14 storage temperature range t stg ?65 155 c
mc9s12h256 device user guide ?v01.20 92 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 5. those pins are internally clamped to v sspll and v ddpll . 6. this pin is clamped low to v sspll , but not clamped high. this pin must be tied low in applications. table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulse per pin positive negative 3 3 machine series resistance r1 0 ? storage capacitance c 200 pf number of pulse per pin positive negative 3 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 v 2 c machine model (mm) v mm 200 v 3 c charge device model (cdm) v cdm 500 v 4c latch-up current at t a = 125 c positive negative i lat +100 ?00 ?a 5c latch-up current at t a = 27 c positive negative i lat +200 ?00 ?a
mc9s12h256 device user guide ?v01.20 93 a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note: please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j )in c can be obtained from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 4.5 5 5.25 v digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage 2 v ddpll 2.35 2.5 2.75 v voltage difference vddx to vddr and vdda ? vddx ?.1 0 0.1 v voltage difference vssx to vssr and vssa ? vssx ?.1 0 0.1 v oscillator f osc 0.5 16 mhz bus frequency f bus 0.5 16 mhz mc9s12h256 c , MC9S12H128 c operating junction temperature range t j ?0 100 c operating ambient temperature range 2 2. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela- tion between ambient temperature t a and device junction temperature t j . t a ?0 27 85 c mc9s12h256 v , MC9S12H128 v operating junction temperature range t j ?0 120 c operating ambient temperature range 2 t a ?0 27 105 c mc9s12h256 m , MC9S12H128 m operating junction temperature range t j ?0 140 c operating ambient temperature range 2 t a ?0 27 125 c
mc9s12h256 device user guide ?v01.20 94 the total power dissipation can be calculated from: p io is the sum of all output currents on i/o ports associated with vddx1,2 and vddm1,2,3. a.1.9 i/o characteristics this section describes the characteristics of all 5v i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-2 ja 54 o c/w 2t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 ja 41 o c/w 3 t thermal resistance lqfp 144, single sided pcb ja 45 o c/w 4t thermal resistance lqfp 144, double sided pcb with 2 internal planes ja 37 o c/w t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? =
mc9s12h256 device user guide ?v01.20 95
mc9s12h256 device user guide ?v01.20 96 table a-6 5v i/o characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 v dd5 + 0.3 v 2 p input low voltage v il v ss5 ?0.3 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4p input leakage current except pu, pv, pw (pins in high impedance input mode) 1 v in = v dd5 or v ss5 i in ?.0 1.0 a 5p input leakage current pu, pv, pw (pins in high impedance input mode) 2 v in = v dd5 or v ss5 i in ?.5 2.5 a 6p output high voltage (pins in output mode, except pu, pv and pw) partial drive i oh = ?.0ma full drive i oh = ?0ma v oh v dd5 ?0.8 v 7p output low voltage (pins in output mode except pu, pv and pw) partial drive i ol = +1.0ma full drive i ol = +10ma v ol 0.8 v 8p output high voltage (pins pu, pv and pw in output mode) i oh = ?0ma v oh v dd5 ?0.32 v dd5 ?0.2 ? 9p output low voltage (pins pu, pv and pw in output mode) i ol = +20ma v ol .2 0.32 v 10 p output rise time (pins pu, pv and pw in output mode with slew control enabled) v dd5 =5v, r load =1k ? , 10% to 90% of v oh -40 c, epp package 25 c, 140 c t r 60 60 120 3 100 180 3 130 ns 11 p output fall time (pins pu, pv and pw in output mode with slew control enabled) v dd5 =5v, r load =1k ? , 10% to 90% of v oh -40 c, epp package 25 c, 140 c t f 60 60 120 3 100 180 3 130 ns 12 p internal pull up device current, tested at v il max. i pul ?30 a 13 p internal pull up device current, tested at v ih min. i puh ?0 a 14 p internal pull down device current, tested at v ih min. i pdh 130 a 15 p internal pull down device current, tested at v il max. i pdl 10 a
mc9s12h256 device user guide ?v01.20 97 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 16mhz bus frequency using a 4mhz oscillator in colpitts mode. production testing is performed using a square wave signal at the extal input. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be 16 d input capacitance c in 6pf 17 t injection current 4 single pin limit total device limit. sum of all injected currents i ics i icp ?.5 ?5 2.5 25 ma 18 p port h, j interrupt input pulse ?tered 5 t pulse 3 s 19 p port h, j interrupt input pulse passed 5 t pulse 10 s notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. 2. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. 3. this only applies to the epp package, non-epp packages retain the 100ns typ and 130ns max spec. 4. refer to section a.1.4 current injection , for more details 5. parameter only applies in stop or pseudo stop mode. table a-6 5v i/o characteristics conditions are shown in table a-4 unless otherwise noted
mc9s12h256 device user guide ?v01.20 98 given. a very good estimate is to take the single chip currents and add the currents due to the external loads. table a-7 supply current characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p run supply currents single chip, internal regulator enabled i dd5 65 ma 2p p wait supply current all modules enabled, pll on only rti enabled 1 i ddw 40 5 ma 3 c p c c p c p c p pseudo stop current (rti and cop disabled) 1, 2 ?0 c 27 c 70 c 85 c c temp option 100 c 105 c v temp option 120 c 125 c m temp option 140 c notes : 1. pll off 2. at those low power dissipation levels t j = t a can be assumed i ddps 360 420 760 800 950 1000 1500 1700 2500 520 2000 3300 4800 a 4 c c c c c c c pseudo stop current (rti and cop enabled) 1, 2 ?0 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps 420 480 820 860 1050 1700 2500 a 5 c p c c p c p c p stop current 2 ?0 c 27 c 70 c 85 c c temp option 100 c 105 c v temp option 120 c 125 c m temp option 140 c i dds 20 40 200 300 550 700 1200 1400 2200 100 1500 2900 4500 a
mc9s12h256 device user guide ?v01.20 99 a.2 atd characteristics this section describes the characteristics of the analog to digital converter. a.2.1 atd operating characteristics the table a-8 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. a.2.2 factors influencing accuracy three factors ?source resistance, source capacitance and current injection ?have an influence on the accuracy of the atd. a.2.2.1 source resistance: due to the input pin leakage current as specified in table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or table a-8 atd operating characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.50v v rh ? rl 4.50 5.00 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles s 5d atd 8-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles s 6d stop recovery time (v dda =5.0 volts) t sr 20 s 7 p reference supply current i ref 0.375 ma
mc9s12h256 device user guide ?v01.20 100 operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. a.2.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 1024 * (c ins ?c inn ). a.2.2.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k*r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table a-9 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s 1k ? 2t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na ?.5 2.5 ma 4 c coupling ratio positive current injection k p 10 ? a/a 5 c coupling ratio negative current injection k n 10 ? a/a
mc9s12h256 device user guide ?v01.20 101 a.2.3 atd accuracy table a-10 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. for the following definitions see also figure a-1 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: table a-10 atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh ?v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl ? 1 counts 3 p 10-bit integral nonlinearity inl ?.5 1.5 2.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae ? 2.0 3 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl ?.5 0.5 counts 7 p 8-bit integral nonlinearity inl ?.0 0.5 1.0 counts 8p 8-bit absolute error 1 ae ?.5 1.0 1.5 counts dnl i () v i v i1 1lsb ------------------------ 1 = inl n () dnl i () i1 = n v n v 0 1lsb ------------------- - n ==
mc9s12h256 device user guide ?v01.20 102 figure a-1 atd accuracy definitions note: figure a-1 shows only definitions, for specification values refer to table a-10 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v i? v i dnl
mc9s12h256 device user guide ?v01.20 103 a.3 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-11 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 burst programming this applies only to the flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: burst programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop --------------------- ? 25 1 f bus ---------- ? + = t bwpgm 4 1 f nvmop --------------------- ? 9 1 f bus ---------- ? + = t brpgm t swpgm 31 t bwpgm ? + =
mc9s12h256 device user guide ?v01.20 104 a.3.1.3 sector erase erasing a 512 byte flash sector or a 4 byte eeprom sector takes: the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. table a-11 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 32 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections a.3.1.1 - a.3.1.4 for guidance. s 5d flash burst programming consecutive word 4 4. urst programming operations are not applicable to eeprom t bwpgm 20.4 2 31 3 s 6d flash burst programming time for 32 words 4 t brpgm 678.4 2 1035.5 3 s 7 p sector erase time t era 20 5 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 26.7 3 ms 8 p mass erase time t mass 100 5 133 3 ms t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ?
mc9s12h256 device user guide ?v01.20 105 the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. table a-12 nvm reliability characteristics note: flash cycling performance is 10 cycles at -40?c to +125?c. data retention is specified for 15 years. note: eeprom cycling performance is 10k cycles at -40?c to 125?c. data retention is specified for 5 years on words after cycling 10k times. however if only 10 cycles are executed on a word the data retention is specified for 15 years. conditions are shown in table a-4 unless otherwise noted num c rating cycles data retention lifetime unit 1 c flash/eeprom (-40?c to +125?c) 10 15 years 2 c eeprom (-40?c to +125?c) 10,000 5 years
mc9s12h256 device user guide ?v01.20 106
mc9s12h256 device user guide ?v01.20 107 a.4 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.4.1 startup table a-13 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. a.4.1.1 por the release level v porr and the assert level v pora are derived from the vdd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.4.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.4.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. table a-13 startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr 2.07 v 2 t por assert level v pora 0.97 v 3 d reset input pulse width, minimum input time pw rstl 2 t osc 4 d startup from reset n rst 192 196 n osc 5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 6 d wait recovery startup time t wrs 14 t cyc
mc9s12h256 device user guide ?v01.20 108 a.4.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. a.4.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.4.2 oscillator the device features an internal colpitts oscillator. by asserting the xclks input during reset this oscillator can be bypassed allowing the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa. table a-14 oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c crystal oscillator range f osc 0.5 16 mhz 2 p startup current i osc 100 a 3 d oscillator start-up time from por or stop n uposc 4100 cyc osc 4 c oscillator start-up time t uposc 8 1 notes : 1. f osc = 4mhz, c = 22pf. 100 2 2. maximum value is for extreme cases using high q, low frequency crystals ms 5 d clock quality check time-out t cqout 0.45 2.5 s 6 p clock monitor failure assert frequency f cmfa 50 100 200 khz 7p external square wave input frequency 3 f ext 0.5 32 mhz 8 d external square wave pulse width low t extl 15 ns 9 d external square wave pulse width high t exth 15 ns 10 d external square wave rise time t extr 1ns 11 d external square wave fall time t extf 1ns 12 d input capacitance extal pin c in 9pf 13 d input capacitance xtal pin c in 13 pf 14 c dc operating bias in colpitts con?uration on extal pin v dcbias 1.1 v
mc9s12h256 device user guide ?v01.20 109 a.4.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.4.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. figure a-2 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-15 . the vco gain at the desired vco output frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. 3. xclks =1 during reset f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k 1 2 ? f cmp c s r c p vddpll k v k 1 e f 1 f vco () k 1 1v ? ----------------------- ? = k i ch k v ? =
mc9s12h256 device user guide ?v01.20 110 the loop bandwidth f c should be chosen to fulfill the gardner? stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above inputs the resistance can be calculated as: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: the stabilization delays shown in table a-15 are dependant on pll operational settings and external component selection (e.g. crystal, xfc filter). a.4.3.2 jitter information the basic functionality of the pll is shown in figure a-2 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-3 . f c 2 f ref ?? 1 2 + + ?? ?? ? ------------------------------------------ 1 50 ------ f c f ref 450 ? -------------- 0.9 = ( ) ; < < n f vco f ref ------------- 2 s y n r 1 + () ? == r 2 nf c ??? k ---------------------------- - = c s 2 2 ? f c r ?? --------------------- - 0.516 f c r ? -------------- - 0.9 = () ; = c s 20 ? c p c s 10 ? ?
mc9s12h256 device user guide ?v01.20 111 figure a-3 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: figure a-4 maximum bus clock jitter approximation 2 3 n? n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? --------------------- 1 t min n () nt nom ? -------------------- - , ?? ?? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n)
mc9s12h256 device user guide ?v01.20 112 this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table a-15 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 32 mhz 3d lock detector transition from acquisition to tracking mode |? trk | 34 % 1 notes : 1. % deviation from target frequency 4 d lock detection |? lock | 0 1.5 % 1 5 d un-lock detection |? unl | 0.5 2.5 % 1 6d lock detector transition from tracking to acquisition mode |? unt | 68 % 1 7c pllon total stabilization delay (auto mode) 2 2. f ref = 4mhz, f bus = 16mhz equivalent f vco = 32mhz: refdv = #$03, synr = #$0f, cs = 4.7nf, cp = 470pf, rs = 10k ? . t stab 0.5 ms 8d pllon acquisition mode stabilization delay 2 t acq 0.3 ms 9d pllon tracking mode stabilization delay 2 t al 0.2 ms 10 p fitting parameter vco loop gain 3 3. k 1 is measured with v xfc = 1.4v and v xfc = 1.7v @ vdd5 = 5.25v k 1 ?20 -224 mhz/v 11 d fitting parameter vco loop frequency f 1 75 mhz 12 p charge pump current acquisition mode | i ch | 20 38.5 60 a 13 p charge pump current tracking mode | i ch | 2 3.5 6 a 14 c jitter ? parameter 1 2 j 1 1.1 % 15 c jitter ? parameter 2 2 j 2 0.13 %
mc9s12h256 device user guide ?v01.20 113 a.5 mscan table a-16 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?tered t wup 2 s 2 p mscan wake-up dominant pulse pass t wup 5 s
mc9s12h256 device user guide ?v01.20 114
mc9s12h256 device user guide ?v01.20 115 a.6 spi a.6.1 master mode figure a-5 and figure a-6 illustrate the master mode timing. timing values are shown in table a-17 . figure a-5 spi master timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 10 4 4 2 9 (cpol = 0) (cpol = 1) 3 11 12 1. if configured as output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
mc9s12h256 device user guide ?v01.20 116 figure a-6 spi master timing (cpha =1) table a-17 spi master mode timing characteristics 1 notes : 1. the numbers 7, 8 in the column labeled ?um are missing. this has been done on purpose to be consistent between the master and the slave timing shown in table a-18 . conditions are shown in table a-4 unless otherwise noted, c load = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 / 2 t sck 3 d enable lag time t lag 1 / 2 t sck 4 d clock (sck) high or low time t wsck t bus ? 30 1024 t bus ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 0ns 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 11 12 10 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 11 3 1. if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
mc9s12h256 device user guide ?v01.20 117 a.6.2 slave mode figure a-7 and figure a-8 illustrate the slave mode timing. timing values are shown in table a-18 . figure a-7 spi slave timing (cpha = 0) figure a-8 spi slave timing (cpha =1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 10 4 4 2 7 (cpol = 0) (cpol = 1) 3 12 slave 12 11 10 11 8 sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 11 12 10 (cpol = 0) (cpol = 1) ss (input) 2 12 11 3 slave 7 8
mc9s12h256 device user guide ?v01.20 118 table a-18 spi slave mode timing characteristics conditions are shown in table a-4 unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 t cyc 3 d enable lag time t lag 1 t cyc 4 d clock (sck) high or low time t wsck t cyc ? 30 ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 25 ns 7 d slave access time t a 1 t cyc 8 d slave miso disable time t dis 1 t cyc 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns
mc9s12h256 device user guide ?v01.20 119 a.7 lcd_32f4b table a.7-19 lcd_32f4b driver electrical characteristics characteristic symbol min. typ. max. unit lcd supply voltage vlcd -0.25 - vddx + 0.25 v lcd output impedance(bp[3:0],fp[31:0]) for outputs to charge to higher voltage level or to gnd 1 notes : 1. outputs measured one at a time, low impedance voltage source connected to the vlcd pin. z bp/fp - - 5.0 kohm lcd output current (bp[3:0],fp[31:0]) for outputs to discharge to lower voltage level except gnd 2 2. outputs measured one at a time, low impedance voltage source connected to the vlcd pin. i bp/fp 50 - - ua
mc9s12h256 device user guide ?v01.20 120
mc9s12h256 device user guide ?v01.20 121 a.8 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure a-9 with the actual timing values shown on table table a-20 . all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. a.8.1 general muxed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs.
mc9s12h256 device user guide ?v01.20 122 figure a-9 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 no a cc 32 ipipo0 ipipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/ w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7
mc9s12h256 device user guide ?v01.20 123 table a-20 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 16.0 mhz 2 p cycle time t cyc 62.5 ns 3 d pulse width, e low pw el 30 ns 4d pulse width, e high 1 pw eh 30 ns 5 d address delay time t ad 8ns 6d address valid time to e rise (pw el ? ad )t av 22 ns 7 d muxed address hold time t mah 2ns 8 d address hold to data valid t ahds 7ns 9 d data hold to address t dha 2ns 10 d read data setup time t dsr 24 ns 11 d read data hold time t dhr 0ns 12 d write data delay time t ddw 7ns 13 d write data hold time t dhw 2ns 14 d write data setup time 1 (pw eh ? ddw ) t dsw 23 ns 15 d address access time 1 (t cyc ? ad ? dsr ) t acca 30 ns 16 d e high access time 1 (pw eh ? dsr ) t acce 6ns 17 d non-multiplexed address delay time t nad 6ns 18 d non-muxed address valid to e rise (pw el ? nad )t nav 26 ns 19 d non-multiplexed address hold time t nah 2ns 20 d chip select delay time t csd 6 + t cyc /4 ns 21 d chip select access time 1 (t cyc ? csd ? dsr ) t accs t cyc /4 ?2 ns 22 d chip select hold time t csh 2ns 23 d chip select negated time t csn 8ns 24 d read/write delay time t rwd 7ns 25 d read/write valid time to e rise (pw el ? rwd )t rwv 25 ns 26 d read/write hold time t rwh 2ns 27 d low strobe delay time t lsd 7ns 28 d low strobe valid time to e rise (pw el ? lsd )t lsv 25 ns 29 d low strobe hold time t lsh 2ns 30 d noacc strobe delay time t nod 7ns 31 d noacc valid time to e rise (pw el ? nod )t nov 25 ns
mc9s12h256 device user guide ?v01.20 124 32 d noacc hold time t noh 2ns 33 d ipipo[1:0] delay time t p0d 27ns 34 d ipipo[1:0] valid time to e rise (pw el ? p0d )t p0v 22 ns 35 d ipipo[1:0] delay time 1 (pw eh ? p1v ) t p1d 225ns 36 d ipipo[1:0] valid time to e fall t p1v 22 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. table a-20 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf num c rating symbol min typ max unit
mc9s12h256 device user guide ?v01.20 125 appendix b package information b.1 general this section provides the physical dimensions of the mc9s12h256 and MC9S12H128 packages.
mc9s12h256 device user guide ?v01.20 126 b.2 112-pin lqfp package figure b-1 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0
mc9s12h256 device user guide ?v01.20 127 b.3 144-pin lqfp package figure b-2 144-pin lqfp mechanical dimensions (case no. 918-03) n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m t l-m dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 0 07 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. case 918-03 issue c 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 0.25 view ab n 0.20 t l-m m l n 2 t t 144x x x=l, m or n
mc9s12h256 device user guide ?v01.20 128
mc9s12h256 device user guide ?v01.20 129 user guide end sheet
mc9s12h256 device user guide ?v01.20 130 how to reach us: home page: www.freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 1-800-521-6274 or 480-768-2130 europe, middle east, and africa: +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-0047, japan 0120-191014 or +81-3-3440-3569 asia/paci?: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2005,2006,2007. all rights reserved. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals? must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

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